projects / openwrt / staging / wigyori.git / blob
? search:


8fd54b1aa323e76112fd986fff6e32c64b136e3a
[openwrt/staging/wigyori.git] /
1 From 79624ca23c53064fefee774a89952a587b72cc01 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.org>
3 Date: Tue, 19 Feb 2019 22:06:59 +0000
4 Subject: [PATCH] PCI: brcmstb: Add Broadcom STB PCIe host controller
5 driver
6
7 This commit adds the basic Broadcom STB PCIe controller. Missing is
8 the ability to process MSI and also handle dma-ranges for inbound
9 memory accesses. These two functionalities are added in subsequent
10 commits.
11
12 The PCIe block contains an MDIO interface. This is a local interface
13 only accessible by the PCIe controller. It cannot be used or shared
14 by any other HW. As such, the small amount of code for this
15 controller is included in this driver as there is little upside to put
16 it elsewhere.
17
18 Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
19 ---
20 drivers/pci/controller/Kconfig | 9 +
21 drivers/pci/controller/Makefile | 2 +-
22 drivers/pci/controller/pcie-brcmstb.c | 1097 +++++++++++++++++++++++++
23 include/soc/brcmstb/memory_api.h | 25 +
24 4 files changed, 1132 insertions(+), 1 deletion(-)
25 create mode 100644 drivers/pci/controller/pcie-brcmstb.c
26 create mode 100644 include/soc/brcmstb/memory_api.h
27
28 --- a/drivers/pci/controller/Kconfig
29 +++ b/drivers/pci/controller/Kconfig
30 @@ -288,5 +288,14 @@ config PCI_HYPERV_INTERFACE
31 The Hyper-V PCI Interface is a helper driver allows other drivers to
32 have a common interface with the Hyper-V PCI frontend driver.
33
34 +config PCIE_BRCMSTB
35 + tristate "Broadcom Brcmstb PCIe platform host driver"
36 + depends on ARCH_BRCMSTB || BMIPS_GENERIC
37 + depends on OF
38 + depends on SOC_BRCMSTB
39 + default ARCH_BRCMSTB || BMIPS_GENERIC
40 + help
41 + Adds support for Broadcom Settop Box PCIe host controller.
42 +
43 source "drivers/pci/controller/dwc/Kconfig"
44 endmenu
45 --- a/drivers/pci/controller/Makefile
46 +++ b/drivers/pci/controller/Makefile
47 @@ -29,11 +29,11 @@ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie
48 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
49 obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
50 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
51 +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
52 obj-$(CONFIG_VMD) += vmd.o
53 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
54 obj-y += dwc/
55
56 -
57 # The following drivers are for devices that use the generic ACPI
58 # pci_root.c driver but don't support standard ECAM config access.
59 # They contain MCFG quirks to replace the generic ECAM accessors with
60 --- /dev/null
61 +++ b/drivers/pci/controller/pcie-brcmstb.c
62 @@ -0,0 +1,1097 @@
63 +// SPDX-License-Identifier: GPL-2.0
64 +/* Copyright (C) 2009 - 2017 Broadcom */
65 +
66 +#include <linux/clk.h>
67 +#include <linux/compiler.h>
68 +#include <linux/delay.h>
69 +#include <linux/init.h>
70 +#include <linux/interrupt.h>
71 +#include <linux/io.h>
72 +#include <linux/ioport.h>
73 +#include <linux/irqdomain.h>
74 +#include <linux/kernel.h>
75 +#include <linux/list.h>
76 +#include <linux/log2.h>
77 +#include <linux/module.h>
78 +#include <linux/of_address.h>
79 +#include <linux/of_irq.h>
80 +#include <linux/of_pci.h>
81 +#include <linux/of_platform.h>
82 +#include <linux/pci.h>
83 +#include <linux/printk.h>
84 +#include <linux/sizes.h>
85 +#include <linux/slab.h>
86 +#include <soc/brcmstb/memory_api.h>
87 +#include <linux/string.h>
88 +#include <linux/types.h>
89 +#include "../pci.h"
90 +
91 +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
92 +#define BRCM_PCIE_CAP_REGS 0x00ac
93 +
94 +/*
95 + * Broadcom Settop Box PCIe Register Offsets. The names are from
96 + * the chip's RDB and we use them here so that a script can correlate
97 + * this code and the RDB to prevent discrepancies.
98 + */
99 +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
100 +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
101 +#define PCIE_RC_DL_MDIO_ADDR 0x1100
102 +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
103 +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
104 +#define PCIE_MISC_MISC_CTRL 0x4008
105 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
106 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
107 +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
108 +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
109 +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
110 +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
111 +#define PCIE_MISC_PCIE_CTRL 0x4064
112 +#define PCIE_MISC_PCIE_STATUS 0x4068
113 +#define PCIE_MISC_REVISION 0x406c
114 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
115 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
116 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
117 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
118 +#define PCIE_INTR2_CPU_BASE 0x4300
119 +
120 +/*
121 + * Broadcom Settop Box PCIe Register Field shift and mask info. The
122 + * names are from the chip's RDB and we use them here so that a script
123 + * can correlate this code and the RDB to prevent discrepancies.
124 + */
125 +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
126 +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
127 +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
128 +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
129 +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
130 +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
131 +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
132 +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
133 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
134 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
135 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
136 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
137 +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
138 +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
139 +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
140 +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
141 +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
142 +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
143 +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
144 +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
145 +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
146 +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
147 +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
148 +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
149 +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
150 +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
151 +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
152 +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
153 +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
154 +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
155 +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
156 +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
157 +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
158 +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
159 +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
160 +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
161 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
162 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
163 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
164 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
165 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
166 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
167 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
168 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
169 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
170 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
171 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
172 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
173 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
174 +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
175 +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
176 +
177 +#define BRCM_NUM_PCIE_OUT_WINS 0x4
178 +#define BRCM_MAX_SCB 0x4
179 +
180 +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
181 +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
182 +
183 +#define BURST_SIZE_128 0
184 +#define BURST_SIZE_256 1
185 +#define BURST_SIZE_512 2
186 +
187 +/* Offsets from PCIE_INTR2_CPU_BASE */
188 +#define STATUS 0x0
189 +#define SET 0x4
190 +#define CLR 0x8
191 +#define MASK_STATUS 0xc
192 +#define MASK_SET 0x10
193 +#define MASK_CLR 0x14
194 +
195 +#define PCIE_BUSNUM_SHIFT 20
196 +#define PCIE_SLOT_SHIFT 15
197 +#define PCIE_FUNC_SHIFT 12
198 +
199 +#if defined(__BIG_ENDIAN)
200 +#define DATA_ENDIAN 2 /* PCIe->DDR inbound traffic */
201 +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound traffic */
202 +#else
203 +#define DATA_ENDIAN 0
204 +#define MMIO_ENDIAN 0
205 +#endif
206 +
207 +#define MDIO_PORT0 0x0
208 +#define MDIO_DATA_MASK 0x7fffffff
209 +#define MDIO_DATA_SHIFT 0x0
210 +#define MDIO_PORT_MASK 0xf0000
211 +#define MDIO_PORT_SHIFT 0x16
212 +#define MDIO_REGAD_MASK 0xffff
213 +#define MDIO_REGAD_SHIFT 0x0
214 +#define MDIO_CMD_MASK 0xfff00000
215 +#define MDIO_CMD_SHIFT 0x14
216 +#define MDIO_CMD_READ 0x1
217 +#define MDIO_CMD_WRITE 0x0
218 +#define MDIO_DATA_DONE_MASK 0x80000000
219 +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
220 +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
221 +#define SSC_REGS_ADDR 0x1100
222 +#define SET_ADDR_OFFSET 0x1f
223 +#define SSC_CNTL_OFFSET 0x2
224 +#define SSC_CNTL_OVRD_EN_MASK 0x8000
225 +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
226 +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
227 +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
228 +#define SSC_STATUS_OFFSET 0x1
229 +#define SSC_STATUS_SSC_MASK 0x400
230 +#define SSC_STATUS_SSC_SHIFT 0xa
231 +#define SSC_STATUS_PLL_LOCK_MASK 0x800
232 +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
233 +
234 +#define IDX_ADDR(pcie) \
235 + ((pcie)->reg_offsets[EXT_CFG_INDEX])
236 +#define DATA_ADDR(pcie) \
237 + ((pcie)->reg_offsets[EXT_CFG_DATA])
238 +#define PCIE_RGR1_SW_INIT_1(pcie) \
239 + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
240 +
241 +enum {
242 + RGR1_SW_INIT_1,
243 + EXT_CFG_INDEX,
244 + EXT_CFG_DATA,
245 +};
246 +
247 +enum {
248 + RGR1_SW_INIT_1_INIT_MASK,
249 + RGR1_SW_INIT_1_INIT_SHIFT,
250 + RGR1_SW_INIT_1_PERST_MASK,
251 + RGR1_SW_INIT_1_PERST_SHIFT,
252 +};
253 +
254 +enum pcie_type {
255 + BCM7425,
256 + BCM7435,
257 + GENERIC,
258 + BCM7278,
259 +};
260 +
261 +struct brcm_window {
262 + dma_addr_t pcie_addr;
263 + phys_addr_t cpu_addr;
264 + dma_addr_t size;
265 +};
266 +
267 +/* Internal PCIe Host Controller Information.*/
268 +struct brcm_pcie {
269 + struct device *dev;
270 + void __iomem *base;
271 + struct list_head resources;
272 + int irq;
273 + struct clk *clk;
274 + struct pci_bus *root_bus;
275 + struct device_node *dn;
276 + int id;
277 + bool suspended;
278 + int num_out_wins;
279 + bool ssc;
280 + int gen;
281 + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
282 + unsigned int rev;
283 + const int *reg_offsets;
284 + const int *reg_field_info;
285 + enum pcie_type type;
286 +};
287 +
288 +struct pcie_cfg_data {
289 + const int *reg_field_info;
290 + const int *offsets;
291 + const enum pcie_type type;
292 +};
293 +
294 +static const int pcie_reg_field_info[] = {
295 + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
296 + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
297 +};
298 +
299 +static const int pcie_reg_field_info_bcm7278[] = {
300 + [RGR1_SW_INIT_1_INIT_MASK] = 0x1,
301 + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x0,
302 +};
303 +
304 +static const int pcie_offset_bcm7425[] = {
305 + [RGR1_SW_INIT_1] = 0x8010,
306 + [EXT_CFG_INDEX] = 0x8300,
307 + [EXT_CFG_DATA] = 0x8304,
308 +};
309 +
310 +static const struct pcie_cfg_data bcm7425_cfg = {
311 + .reg_field_info = pcie_reg_field_info,
312 + .offsets = pcie_offset_bcm7425,
313 + .type = BCM7425,
314 +};
315 +
316 +static const int pcie_offsets[] = {
317 + [RGR1_SW_INIT_1] = 0x9210,
318 + [EXT_CFG_INDEX] = 0x9000,
319 + [EXT_CFG_DATA] = 0x9004,
320 +};
321 +
322 +static const struct pcie_cfg_data bcm7435_cfg = {
323 + .reg_field_info = pcie_reg_field_info,
324 + .offsets = pcie_offsets,
325 + .type = BCM7435,
326 +};
327 +
328 +static const struct pcie_cfg_data generic_cfg = {
329 + .reg_field_info = pcie_reg_field_info,
330 + .offsets = pcie_offsets,
331 + .type = GENERIC,
332 +};
333 +
334 +static const int pcie_offset_bcm7278[] = {
335 + [RGR1_SW_INIT_1] = 0xc010,
336 + [EXT_CFG_INDEX] = 0x9000,
337 + [EXT_CFG_DATA] = 0x9004,
338 +};
339 +
340 +static const struct pcie_cfg_data bcm7278_cfg = {
341 + .reg_field_info = pcie_reg_field_info_bcm7278,
342 + .offsets = pcie_offset_bcm7278,
343 + .type = BCM7278,
344 +};
345 +
346 +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
347 + int where);
348 +
349 +static struct pci_ops brcm_pcie_ops = {
350 + .map_bus = brcm_pcie_map_conf,
351 + .read = pci_generic_config_read,
352 + .write = pci_generic_config_write,
353 +};
354 +
355 +#if defined(CONFIG_MIPS)
356 +/* Broadcom MIPs HW implicitly does the swapping if necessary */
357 +#define bcm_readl(a) __raw_readl(a)
358 +#define bcm_writel(d, a) __raw_writel(d, a)
359 +#define bcm_readw(a) __raw_readw(a)
360 +#define bcm_writew(d, a) __raw_writew(d, a)
361 +#else
362 +#define bcm_readl(a) readl(a)
363 +#define bcm_writel(d, a) writel(d, a)
364 +#define bcm_readw(a) readw(a)
365 +#define bcm_writew(d, a) writew(d, a)
366 +#endif
367 +
368 +/* These macros extract/insert fields to host controller's register set. */
369 +#define RD_FLD(base, reg, field) \
370 + rd_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
371 +#define WR_FLD(base, reg, field, val) \
372 + wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
373 +#define WR_FLD_RB(base, reg, field, val) \
374 + wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
375 +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
376 + wr_fld(base + reg + off, reg##_##field##_MASK, \
377 + reg##_##field##_SHIFT, val)
378 +#define EXTRACT_FIELD(val, reg, field) \
379 + ((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
380 +#define INSERT_FIELD(val, reg, field, field_val) \
381 + ((val & ~reg##_##field##_MASK) | \
382 + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
383 +
384 +static phys_addr_t scb_size[BRCM_MAX_SCB];
385 +static int num_memc;
386 +static int num_pcie;
387 +static DEFINE_MUTEX(brcm_pcie_lock);
388 +
389 +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
390 +{
391 + return (bcm_readl(p) & mask) >> shift;
392 +}
393 +
394 +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
395 +{
396 + u32 reg = bcm_readl(p);
397 +
398 + reg = (reg & ~mask) | ((val << shift) & mask);
399 + bcm_writel(reg, p);
400 +}
401 +
402 +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
403 +{
404 + wr_fld(p, mask, shift, val);
405 + (void)bcm_readl(p);
406 +}
407 +
408 +static const char *link_speed_to_str(int s)
409 +{
410 + switch (s) {
411 + case 1:
412 + return "2.5";
413 + case 2:
414 + return "5.0";
415 + case 3:
416 + return "8.0";
417 + default:
418 + break;
419 + }
420 + return "???";
421 +}
422 +
423 +/*
424 + * The roundup_pow_of_two() from log2.h invokes
425 + * __roundup_pow_of_two(unsigned long), but we really need a
426 + * such a function to take a native u64 since unsigned long
427 + * is 32 bits on some configurations. So we provide this helper
428 + * function below.
429 + */
430 +static u64 roundup_pow_of_two_64(u64 n)
431 +{
432 + return 1ULL << fls64(n - 1);
433 +}
434 +
435 +/*
436 + * This is to convert the size of the inbound "BAR" region to the
437 + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
438 + */
439 +int encode_ibar_size(u64 size)
440 +{
441 + int log2_in = ilog2(size);
442 +
443 + if (log2_in >= 12 && log2_in <= 15)
444 + /* Covers 4KB to 32KB (inclusive) */
445 + return (log2_in - 12) + 0x1c;
446 + else if (log2_in >= 16 && log2_in <= 37)
447 + /* Covers 64KB to 32GB, (inclusive) */
448 + return log2_in - 15;
449 + /* Something is awry so disable */
450 + return 0;
451 +}
452 +
453 +static u32 mdio_form_pkt(int port, int regad, int cmd)
454 +{
455 + u32 pkt = 0;
456 +
457 + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
458 + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
459 + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
460 +
461 + return pkt;
462 +}
463 +
464 +/* negative return value indicates error */
465 +static int mdio_read(void __iomem *base, u8 port, u8 regad)
466 +{
467 + int tries;
468 + u32 data;
469 +
470 + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
471 + base + PCIE_RC_DL_MDIO_ADDR);
472 + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
473 +
474 + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
475 + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
476 + udelay(10);
477 + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
478 + }
479 +
480 + return MDIO_RD_DONE(data)
481 + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
482 + : -EIO;
483 +}
484 +
485 +/* negative return value indicates error */
486 +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
487 +{
488 + int tries;
489 + u32 data;
490 +
491 + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
492 + base + PCIE_RC_DL_MDIO_ADDR);
493 + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
494 + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
495 + base + PCIE_RC_DL_MDIO_WR_DATA);
496 +
497 + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
498 + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
499 + udelay(10);
500 + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
501 + }
502 +
503 + return MDIO_WT_DONE(data) ? 0 : -EIO;
504 +}
505 +
506 +/*
507 + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
508 + * return value indicates error.
509 + */
510 +static int set_ssc(void __iomem *base)
511 +{
512 + int tmp;
513 + u16 wrdata;
514 + int pll, ssc;
515 +
516 + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
517 + if (tmp < 0)
518 + return tmp;
519 +
520 + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
521 + if (tmp < 0)
522 + return tmp;
523 +
524 + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
525 + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
526 + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
527 + if (tmp < 0)
528 + return tmp;
529 +
530 + usleep_range(1000, 2000);
531 + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
532 + if (tmp < 0)
533 + return tmp;
534 +
535 + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
536 + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
537 +
538 + return (ssc && pll) ? 0 : -EIO;
539 +}
540 +
541 +/* Limits operation to a specific generation (1, 2, or 3) */
542 +static void set_gen(void __iomem *base, int gen)
543 +{
544 + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
545 + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
546 +
547 + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
548 + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
549 +
550 + lnkctl2 = (lnkctl2 & ~0xf) | gen;
551 + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
552 +}
553 +
554 +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
555 + unsigned int win, phys_addr_t cpu_addr,
556 + dma_addr_t pcie_addr, dma_addr_t size)
557 +{
558 + void __iomem *base = pcie->base;
559 + phys_addr_t cpu_addr_mb, limit_addr_mb;
560 + u32 tmp;
561 +
562 + /* Set the base of the pcie_addr window */
563 + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
564 + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
565 + bcm_writel(upper_32_bits(pcie_addr),
566 + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
567 +
568 + cpu_addr_mb = cpu_addr >> 20;
569 + limit_addr_mb = (cpu_addr + size - 1) >> 20;
570 +
571 + /* Write the addr base low register */
572 + WR_FLD_WITH_OFFSET(base, (win * 4),
573 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
574 + BASE, cpu_addr_mb);
575 + /* Write the addr limit low register */
576 + WR_FLD_WITH_OFFSET(base, (win * 4),
577 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
578 + LIMIT, limit_addr_mb);
579 +
580 + if (pcie->type != BCM7435 && pcie->type != BCM7425) {
581 + /* Write the cpu addr high register */
582 + tmp = (u32)(cpu_addr_mb >>
583 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
584 + WR_FLD_WITH_OFFSET(base, (win * 8),
585 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
586 + BASE, tmp);
587 + /* Write the cpu limit high register */
588 + tmp = (u32)(limit_addr_mb >>
589 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
590 + WR_FLD_WITH_OFFSET(base, (win * 8),
591 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
592 + LIMIT, tmp);
593 + }
594 +}
595 +
596 +/* Configuration space read/write support */
597 +static int cfg_index(int busnr, int devfn, int reg)
598 +{
599 + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
600 + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
601 + | (busnr << PCIE_BUSNUM_SHIFT)
602 + | (reg & ~3);
603 +}
604 +
605 +/* The controller is capable of serving in both RC and EP roles */
606 +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
607 +{
608 + void __iomem *base = pcie->base;
609 + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
610 +
611 + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
612 +}
613 +
614 +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
615 +{
616 + void __iomem *base = pcie->base;
617 + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
618 + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
619 + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
620 +
621 + return (dla && plu) ? true : false;
622 +}
623 +
624 +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
625 + int where)
626 +{
627 + struct brcm_pcie *pcie = bus->sysdata;
628 + void __iomem *base = pcie->base;
629 + int idx;
630 +
631 + /* Accesses to the RC go right to the RC registers if slot==0 */
632 + if (pci_is_root_bus(bus))
633 + return PCI_SLOT(devfn) ? NULL : base + where;
634 +
635 + /* For devices, write to the config space index register */
636 + idx = cfg_index(bus->number, devfn, where);
637 + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
638 + return base + DATA_ADDR(pcie) + (where & 0x3);
639 +}
640 +
641 +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
642 + unsigned int val)
643 +{
644 + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
645 + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
646 +
647 + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
648 +}
649 +
650 +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
651 + unsigned int val)
652 +{
653 + if (pcie->type != BCM7278)
654 + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
655 + PCIE_RGR1_SW_INIT_1_PERST_MASK,
656 + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
657 + else
658 + /* Assert = 0, de-assert = 1 on 7278 */
659 + WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val);
660 +}
661 +
662 +static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
663 +{
664 + int i, ret = 0;
665 +
666 + mutex_lock(&brcm_pcie_lock);
667 + if (num_pcie > 0) {
668 + num_pcie++;
669 + goto done;
670 + }
671 +
672 + /* Determine num_memc and their sizes */
673 + for (i = 0, num_memc = 0; i < BRCM_MAX_SCB; i++) {
674 + u64 size = brcmstb_memory_memc_size(i);
675 +
676 + if (size == (u64)-1) {
677 + dev_err(pcie->dev, "cannot get memc%d size\n", i);
678 + ret = -EINVAL;
679 + goto done;
680 + } else if (size) {
681 + scb_size[i] = roundup_pow_of_two_64(size);
682 + num_memc++;
683 + } else {
684 + break;
685 + }
686 + }
687 + if (!ret && num_memc == 0) {
688 + ret = -EINVAL;
689 + goto done;
690 + }
691 +
692 + num_pcie++;
693 +done:
694 + mutex_unlock(&brcm_pcie_lock);
695 + return ret;
696 +}
697 +
698 +static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
699 +{
700 + mutex_lock(&brcm_pcie_lock);
701 + if (--num_pcie == 0)
702 + num_memc = 0;
703 + mutex_unlock(&brcm_pcie_lock);
704 +}
705 +
706 +static int brcm_pcie_parse_request_of_pci_ranges(struct brcm_pcie *pcie)
707 +{
708 + struct resource_entry *win;
709 + int ret;
710 +
711 + ret = devm_of_pci_get_host_bridge_resources(pcie->dev, 0, 0xff,
712 + &pcie->resources, NULL);
713 + if (ret) {
714 + dev_err(pcie->dev, "failed to get host resources\n");
715 + return ret;
716 + }
717 +
718 + resource_list_for_each_entry(win, &pcie->resources) {
719 + struct resource *parent, *res = win->res;
720 + dma_addr_t offset = (dma_addr_t)win->offset;
721 +
722 + if (resource_type(res) == IORESOURCE_IO) {
723 + parent = &ioport_resource;
724 + } else if (resource_type(res) == IORESOURCE_MEM) {
725 + if (pcie->num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
726 + dev_err(pcie->dev, "too many outbound wins\n");
727 + return -EINVAL;
728 + }
729 + pcie->out_wins[pcie->num_out_wins].cpu_addr
730 + = (phys_addr_t)res->start;
731 + pcie->out_wins[pcie->num_out_wins].pcie_addr
732 + = (dma_addr_t)(res->start
733 + - (phys_addr_t)offset);
734 + pcie->out_wins[pcie->num_out_wins].size
735 + = (dma_addr_t)(res->end - res->start + 1);
736 + pcie->num_out_wins++;
737 + parent = &iomem_resource;
738 + } else {
739 + continue;
740 + }
741 +
742 + ret = devm_request_resource(pcie->dev, parent, res);
743 + if (ret) {
744 + dev_err(pcie->dev, "failed to get res %pR\n", res);
745 + return ret;
746 + }
747 + }
748 + return 0;
749 +}
750 +
751 +static int brcm_pcie_setup(struct brcm_pcie *pcie)
752 +{
753 + void __iomem *base = pcie->base;
754 + unsigned int scb_size_val;
755 + u64 rc_bar2_offset, rc_bar2_size, total_mem_size = 0;
756 + u32 tmp, burst;
757 + int i, j, ret, limit;
758 + u16 nlw, cls, lnksta;
759 + bool ssc_good = false;
760 + struct device *dev = pcie->dev;
761 +
762 + /* Reset the bridge */
763 + brcm_pcie_bridge_sw_init_set(pcie, 1);
764 +
765 + /*
766 + * Ensure that the fundamental reset is asserted, except for 7278,
767 + * which fails if we do this.
768 + */
769 + if (pcie->type != BCM7278)
770 + brcm_pcie_perst_set(pcie, 1);
771 +
772 + usleep_range(100, 200);
773 +
774 + /* Take the bridge out of reset */
775 + brcm_pcie_bridge_sw_init_set(pcie, 0);
776 +
777 + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
778 + /* Wait for SerDes to be stable */
779 + usleep_range(100, 200);
780 +
781 + /* Grab the PCIe hw revision number */
782 + tmp = bcm_readl(base + PCIE_MISC_REVISION);
783 + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
784 +
785 + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
786 + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
787 + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
788 + burst = (pcie->type == GENERIC || pcie->type == BCM7278)
789 + ? BURST_SIZE_512 : BURST_SIZE_256;
790 + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, burst);
791 + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
792 +
793 + /*
794 + * Set up inbound memory view for the EP (called RC_BAR2,
795 + * not to be confused with the BARs that are advertised by
796 + * the EP).
797 + */
798 + for (i = 0; i < num_memc; i++)
799 + total_mem_size += scb_size[i];
800 +
801 + /*
802 + * The PCIe host controller by design must set the inbound
803 + * viewport to be a contiguous arrangement of all of the
804 + * system's memory. In addition, its size mut be a power of
805 + * two. To further complicate matters, the viewport must
806 + * start on a pcie-address that is aligned on a multiple of its
807 + * size. If a portion of the viewport does not represent
808 + * system memory -- e.g. 3GB of memory requires a 4GB viewport
809 + * -- we can map the outbound memory in or after 3GB and even
810 + * though the viewport will overlap the outbound memory the
811 + * controller will know to send outbound memory downstream and
812 + * everything else upstream.
813 + */
814 + rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
815 +
816 + /*
817 + * Set simple configuration based on memory sizes
818 + * only. We always start the viewport at address 0.
819 + */
820 + rc_bar2_offset = 0;
821 +
822 + tmp = lower_32_bits(rc_bar2_offset);
823 + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
824 + encode_ibar_size(rc_bar2_size));
825 + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
826 + bcm_writel(upper_32_bits(rc_bar2_offset),
827 + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
828 +
829 + scb_size_val = scb_size[0]
830 + ? ilog2(scb_size[0]) - 15 : 0xf; /* 0xf is 1GB */
831 + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
832 +
833 + if (num_memc > 1) {
834 + scb_size_val = scb_size[1]
835 + ? ilog2(scb_size[1]) - 15 : 0xf; /* 0xf is 1GB */
836 + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val);
837 + }
838 +
839 + if (num_memc > 2) {
840 + scb_size_val = scb_size[2]
841 + ? ilog2(scb_size[2]) - 15 : 0xf; /* 0xf is 1GB */
842 + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val);
843 + }
844 +
845 + /* disable the PCIe->GISB memory window (RC_BAR1) */
846 + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
847 +
848 + /* disable the PCIe->SCB memory window (RC_BAR3) */
849 + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
850 +
851 + if (!pcie->suspended) {
852 + /* clear any interrupts we find on boot */
853 + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
854 + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
855 + }
856 +
857 + /* Mask all interrupts since we are not handling any yet */
858 + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
859 + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
860 +
861 + if (pcie->gen)
862 + set_gen(base, pcie->gen);
863 +
864 + /* Unassert the fundamental reset */
865 + brcm_pcie_perst_set(pcie, 0);
866 +
867 + /*
868 + * Give the RC/EP time to wake up, before trying to configure RC.
869 + * Intermittently check status for link-up, up to a total of 100ms
870 + * when we don't know if the device is there, and up to 1000ms if
871 + * we do know the device is there.
872 + */
873 + limit = pcie->suspended ? 1000 : 100;
874 + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
875 + j += i, i = i * 2)
876 + msleep(i + j > limit ? limit - j : i);
877 +
878 + if (!brcm_pcie_link_up(pcie)) {
879 + dev_info(dev, "link down\n");
880 + return -ENODEV;
881 + }
882 +
883 + if (!brcm_pcie_rc_mode(pcie)) {
884 + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
885 + return -EINVAL;
886 + }
887 +
888 + for (i = 0; i < pcie->num_out_wins; i++)
889 + brcm_pcie_set_outbound_win(pcie, i, pcie->out_wins[i].cpu_addr,
890 + pcie->out_wins[i].pcie_addr,
891 + pcie->out_wins[i].size);
892 +
893 + /*
894 + * For config space accesses on the RC, show the right class for
895 + * a PCIe-PCIe bridge (the default setting is to be EP mode).
896 + */
897 + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
898 +
899 + if (pcie->ssc) {
900 + ret = set_ssc(base);
901 + if (ret == 0)
902 + ssc_good = true;
903 + else
904 + dev_err(dev, "failed attempt to enter ssc mode\n");
905 + }
906 +
907 + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
908 + cls = lnksta & PCI_EXP_LNKSTA_CLS;
909 + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
910 + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
911 + nlw, ssc_good ? "(SSC)" : "(!SSC)");
912 +
913 + /* PCIe->SCB endian mode for BAR */
914 + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
915 + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
916 + ENDIAN_MODE_BAR2, DATA_ENDIAN);
917 +
918 + /*
919 + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
920 + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
921 + */
922 + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
923 +
924 + return 0;
925 +}
926 +
927 +/* L23 is a low-power PCIe link state */
928 +static void enter_l23(struct brcm_pcie *pcie)
929 +{
930 + void __iomem *base = pcie->base;
931 + int tries, l23;
932 +
933 + /* assert request for L23 */
934 + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
935 + /* poll L23 status */
936 + for (tries = 0, l23 = 0; tries < 1000 && !l23; tries++)
937 + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
938 + if (!l23)
939 + dev_err(pcie->dev, "failed to enter L23\n");
940 +}
941 +
942 +static void turn_off(struct brcm_pcie *pcie)
943 +{
944 + void __iomem *base = pcie->base;
945 +
946 + if (brcm_pcie_link_up(pcie))
947 + enter_l23(pcie);
948 + /* Assert fundamental reset */
949 + brcm_pcie_perst_set(pcie, 1);
950 + /* Deassert request for L23 in case it was asserted */
951 + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
952 + /* Turn off SerDes */
953 + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
954 + /* Shutdown PCIe bridge */
955 + brcm_pcie_bridge_sw_init_set(pcie, 1);
956 +}
957 +
958 +static int brcm_pcie_suspend(struct device *dev)
959 +{
960 + struct brcm_pcie *pcie = dev_get_drvdata(dev);
961 +
962 + turn_off(pcie);
963 + clk_disable_unprepare(pcie->clk);
964 + pcie->suspended = true;
965 +
966 + return 0;
967 +}
968 +
969 +static int brcm_pcie_resume(struct device *dev)
970 +{
971 + struct brcm_pcie *pcie = dev_get_drvdata(dev);
972 + void __iomem *base;
973 + int ret;
974 +
975 + base = pcie->base;
976 + clk_prepare_enable(pcie->clk);
977 +
978 + /* Take bridge out of reset so we can access the SerDes reg */
979 + brcm_pcie_bridge_sw_init_set(pcie, 0);
980 +
981 + /* Turn on SerDes */
982 + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
983 + /* Wait for SerDes to be stable */
984 + usleep_range(100, 200);
985 +
986 + ret = brcm_pcie_setup(pcie);
987 + if (ret)
988 + return ret;
989 +
990 + pcie->suspended = false;
991 +
992 + return 0;
993 +}
994 +
995 +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
996 +{
997 + turn_off(pcie);
998 + clk_disable_unprepare(pcie->clk);
999 + clk_put(pcie->clk);
1000 + brcm_pcie_remove_controller(pcie);
1001 +}
1002 +
1003 +static int brcm_pcie_remove(struct platform_device *pdev)
1004 +{
1005 + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1006 +
1007 + pci_stop_root_bus(pcie->root_bus);
1008 + pci_remove_root_bus(pcie->root_bus);
1009 + _brcm_pcie_remove(pcie);
1010 +
1011 + return 0;
1012 +}
1013 +
1014 +static const struct of_device_id brcm_pcie_match[] = {
1015 + { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1016 + { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1017 + { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1018 + { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1019 + {},
1020 +};
1021 +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
1022 +
1023 +static int brcm_pcie_probe(struct platform_device *pdev)
1024 +{
1025 + struct device_node *dn = pdev->dev.of_node;
1026 + const struct of_device_id *of_id;
1027 + const struct pcie_cfg_data *data;
1028 + int ret;
1029 + struct brcm_pcie *pcie;
1030 + struct resource *res;
1031 + void __iomem *base;
1032 + u32 tmp;
1033 + struct pci_host_bridge *bridge;
1034 + struct pci_bus *child;
1035 +
1036 + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1037 + if (!bridge)
1038 + return -ENOMEM;
1039 +
1040 + pcie = pci_host_bridge_priv(bridge);
1041 + INIT_LIST_HEAD(&pcie->resources);
1042 +
1043 + of_id = of_match_node(brcm_pcie_match, dn);
1044 + if (!of_id) {
1045 + dev_err(&pdev->dev, "failed to look up compatible string\n");
1046 + return -EINVAL;
1047 + }
1048 +
1049 + if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
1050 + dev_err(&pdev->dev, "cannot yet handle dma-ranges\n");
1051 + return -EINVAL;
1052 + }
1053 +
1054 + data = of_id->data;
1055 + pcie->reg_offsets = data->offsets;
1056 + pcie->reg_field_info = data->reg_field_info;
1057 + pcie->type = data->type;
1058 + pcie->dn = dn;
1059 + pcie->dev = &pdev->dev;
1060 +
1061 + /* We use the domain number as our controller number */
1062 + pcie->id = of_get_pci_domain_nr(dn);
1063 + if (pcie->id < 0)
1064 + return pcie->id;
1065 +
1066 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1067 + if (!res)
1068 + return -EINVAL;
1069 +
1070 + base = devm_ioremap_resource(&pdev->dev, res);
1071 + if (IS_ERR(base))
1072 + return PTR_ERR(base);
1073 +
1074 + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
1075 + if (IS_ERR(pcie->clk)) {
1076 + dev_err(&pdev->dev, "could not get clock\n");
1077 + pcie->clk = NULL;
1078 + }
1079 + pcie->base = base;
1080 +
1081 + ret = of_pci_get_max_link_speed(dn);
1082 + pcie->gen = (ret < 0) ? 0 : ret;
1083 +
1084 + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
1085 +
1086 + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
1087 + if (ret == 0)
1088 + /* keep going, as we don't use this intr yet */
1089 + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
1090 + else
1091 + pcie->irq = ret;
1092 +
1093 + ret = brcm_pcie_parse_request_of_pci_ranges(pcie);
1094 + if (ret)
1095 + return ret;
1096 +
1097 + ret = clk_prepare_enable(pcie->clk);
1098 + if (ret) {
1099 + dev_err(&pdev->dev, "could not enable clock\n");
1100 + return ret;
1101 + }
1102 +
1103 + ret = brcm_pcie_add_controller(pcie);
1104 + if (ret)
1105 + return ret;
1106 +
1107 + ret = brcm_pcie_setup(pcie);
1108 + if (ret)
1109 + goto fail;
1110 +
1111 + list_splice_init(&pcie->resources, &bridge->windows);
1112 + bridge->dev.parent = &pdev->dev;
1113 + bridge->busnr = 0;
1114 + bridge->ops = &brcm_pcie_ops;
1115 + bridge->sysdata = pcie;
1116 + bridge->map_irq = of_irq_parse_and_map_pci;
1117 + bridge->swizzle_irq = pci_common_swizzle;
1118 +
1119 + ret = pci_scan_root_bus_bridge(bridge);
1120 + if (ret < 0) {
1121 + dev_err(pcie->dev, "Scanning root bridge failed\n");
1122 + goto fail;
1123 + }
1124 +
1125 + pci_assign_unassigned_bus_resources(bridge->bus);
1126 + list_for_each_entry(child, &bridge->bus->children, node)
1127 + pcie_bus_configure_settings(child);
1128 + pci_bus_add_devices(bridge->bus);
1129 + platform_set_drvdata(pdev, pcie);
1130 + pcie->root_bus = bridge->bus;
1131 +
1132 + return 0;
1133 +
1134 +fail:
1135 + _brcm_pcie_remove(pcie);
1136 + return ret;
1137 +}
1138 +
1139 +static const struct dev_pm_ops brcm_pcie_pm_ops = {
1140 + .suspend_noirq = brcm_pcie_suspend,
1141 + .resume_noirq = brcm_pcie_resume,
1142 +};
1143 +
1144 +static struct platform_driver brcm_pcie_driver = {
1145 + .probe = brcm_pcie_probe,
1146 + .remove = brcm_pcie_remove,
1147 + .driver = {
1148 + .name = "brcm-pcie",
1149 + .owner = THIS_MODULE,
1150 + .of_match_table = brcm_pcie_match,
1151 + .pm = &brcm_pcie_pm_ops,
1152 + },
1153 +};
1154 +
1155 +module_platform_driver(brcm_pcie_driver);
1156 +
1157 +MODULE_LICENSE("GPL v2");
1158 +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
1159 +MODULE_AUTHOR("Broadcom");
1160 --- /dev/null
1161 +++ b/include/soc/brcmstb/memory_api.h
1162 @@ -0,0 +1,25 @@
1163 +#ifndef __MEMORY_API_H
1164 +#define __MEMORY_API_H
1165 +
1166 +/*
1167 + * Bus Interface Unit control register setup, must happen early during boot,
1168 + * before SMP is brought up, called by machine entry point.
1169 + */
1170 +void brcmstb_biuctrl_init(void);
1171 +
1172 +#ifdef CONFIG_SOC_BRCMSTB
1173 +int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa);
1174 +u64 brcmstb_memory_memc_size(int memc);
1175 +#else
1176 +static inline int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
1177 +{
1178 + return -EINVAL;
1179 +}
1180 +
1181 +static inline u64 brcmstb_memory_memc_size(int memc)
1182 +{
1183 + return -1;
1184 +}
1185 +#endif
1186 +
1187 +#endif /* __MEMORY_API_H */
Staging tree of Zoltan Herpai