94784f7885d82f94f3e3d91e6cf14026a8536d70
[openwrt/staging/jow.git] /
1 From 612616e6381929e7f9e303f8b8ad3655cc101516 Mon Sep 17 00:00:00 2001
2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
3 Date: Mon, 19 Jun 2023 06:09:33 +0200
4 Subject: [PATCH 1/9] dt-bindings: clock: add mtmips SoCs system controller
5
6 Adds device tree binding documentation for system controller node present
7 in Mediatek MIPS and Ralink SOCs. This node is a clock and reset provider
8 for the rest of the world. This covers RT2880, RT3050, RT3052, RT3350,
9 RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs.
10
11 Reviewed-by: Rob Herring <robh@kernel.org>
12 Acked-by: Stephen Boyd <sboyd@kernel.org>
13 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 ---
16 .../bindings/clock/mediatek,mtmips-sysc.yaml | 64 ++++++++++++++++++++++
17 1 file changed, 64 insertions(+)
18 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
19
20 --- /dev/null
21 +++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
22 @@ -0,0 +1,64 @@
23 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
24 +%YAML 1.2
25 +---
26 +$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
27 +$schema: http://devicetree.org/meta-schemas/core.yaml#
28 +
29 +title: MTMIPS SoCs System Controller
30 +
31 +maintainers:
32 + - Sergio Paracuellos <sergio.paracuellos@gmail.com>
33 +
34 +description: |
35 + MediaTek MIPS and Ralink SoCs provides a system controller to allow
36 + to access to system control registers. These registers include clock
37 + and reset related ones so this node is both clock and reset provider
38 + for the rest of the world.
39 +
40 + These SoCs have an XTAL from where the cpu clock is
41 + provided as well as derived clocks for the bus and the peripherals.
42 +
43 +properties:
44 + compatible:
45 + items:
46 + - enum:
47 + - ralink,mt7620-sysc
48 + - ralink,mt7628-sysc
49 + - ralink,mt7688-sysc
50 + - ralink,rt2880-sysc
51 + - ralink,rt3050-sysc
52 + - ralink,rt3052-sysc
53 + - ralink,rt3352-sysc
54 + - ralink,rt3883-sysc
55 + - ralink,rt5350-sysc
56 + - const: syscon
57 +
58 + reg:
59 + maxItems: 1
60 +
61 + '#clock-cells':
62 + description:
63 + The first cell indicates the clock number.
64 + const: 1
65 +
66 + '#reset-cells':
67 + description:
68 + The first cell indicates the reset bit within the register.
69 + const: 1
70 +
71 +required:
72 + - compatible
73 + - reg
74 + - '#clock-cells'
75 + - '#reset-cells'
76 +
77 +additionalProperties: false
78 +
79 +examples:
80 + - |
81 + syscon@0 {
82 + compatible = "ralink,rt5350-sysc", "syscon";
83 + reg = <0x0 0x100>;
84 + #clock-cells = <1>;
85 + #reset-cells = <1>;
86 + };