git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 1a82d7080001d395563ad8266d120d4cf63ad0a5 Mon Sep 17 00:00:00 2001
   2 From: Shawn Guo <shawn.guo@linaro.org>
   3 Date: Wed, 29 Sep 2021 11:42:46 +0800
   4 Subject: [PATCH] arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY
   5  child node
   6
   7 '#clock-cells' is a required property of QMP PHY child node, not itself.
   8 Move it to fix the dtbs_check warnings.
   9
  10 There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because
  11 child nodes already have the property.
  12
  13 Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
  14 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  15 Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org
  16 ---
  17  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
  18  1 file changed, 2 insertions(+), 2 deletions(-)
  19
  20 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  21 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  22 @@ -91,7 +91,6 @@
  23                 ssphy_1: phy@58000 {
  24                         compatible = "qcom,ipq8074-qmp-usb3-phy";
  25                         reg = <0x00058000 0x1c4>;
  26 -                       #clock-cells = <1>;
  27                         #address-cells = <1>;
  28                         #size-cells = <1>;
  29                         ranges;
  30 @@ -112,6 +111,7 @@
  31                                       <0x00058800 0x1f8>,     /* PCS  */
  32                                       <0x00058600 0x044>;     /* PCS misc*/
  33                                 #phy-cells = <0>;
  34 +                               #clock-cells = <1>;
  35                                 clocks = <&gcc GCC_USB1_PIPE_CLK>;
  36                                 clock-names = "pipe0";
  37                                 clock-output-names = "usb3phy_1_cc_pipe_clk";
  38 @@ -134,7 +134,6 @@
  39                 ssphy_0: phy@78000 {
  40                         compatible = "qcom,ipq8074-qmp-usb3-phy";
  41                         reg = <0x00078000 0x1c4>;
  42 -                       #clock-cells = <1>;
  43                         #address-cells = <1>;
  44                         #size-cells = <1>;
  45                         ranges;
  46 @@ -155,6 +154,7 @@
  47                                       <0x00078800 0x1f8>,     /* PCS  */
  48                                       <0x00078600 0x044>;     /* PCS misc*/
  49                                 #phy-cells = <0>;
  50 +                               #clock-cells = <1>;
  51                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
  52                                 clock-names = "pipe0";
  53                                 clock-output-names = "usb3phy_0_cc_pipe_clk";