git.openwrt.org Git - openwrt/staging/linusw.git/blob

   1 From 3c398513990aa0edc5b9ebfbdd2395623562c6e4 Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Thu, 25 Jun 2020 18:48:40 +0100
   4 Subject: [PATCH] vc4_hdmi: Remove firmware logic for MAI threshold
   5  setting
   6
   7 This was a workaround for bugs in hardware on earlier Pi models
   8 and wasn't totally successful.
   9
  10 It makes audio quality worse on a Pi4 at the higher sample rates
  11
  12 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  13 ---
  14  drivers/gpu/drm/vc4/vc4_hdmi.c | 22 ++++++----------------
  15  1 file changed, 6 insertions(+), 16 deletions(-)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  19 @@ -1083,22 +1083,12 @@ static int vc4_hdmi_audio_prepare(struct
  20         audio_packet_config |= VC4_SET_FIELD(channel_mask,
  21                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
  22
  23 -       /* Set the MAI threshold.  This logic mimics the firmware's. */
  24 -       if (vc4_hdmi->audio.samplerate > 96000) {
  25 -               HDMI_WRITE(HDMI_MAI_THR,
  26 -                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
  27 -                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
  28 -       } else if (vc4_hdmi->audio.samplerate > 48000) {
  29 -               HDMI_WRITE(HDMI_MAI_THR,
  30 -                          VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
  31 -                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
  32 -       } else {
  33 -               HDMI_WRITE(HDMI_MAI_THR,
  34 -                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
  35 -                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
  36 -                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
  37 -                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
  38 -       }
  39 +       /* Set the MAI threshold */
  40 +       HDMI_WRITE(HDMI_MAI_THR,
  41 +                  VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
  42 +                  VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
  43 +                  VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
  44 +                  VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
  45
  46         HDMI_WRITE(HDMI_MAI_CONFIG,
  47                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |