git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From 62a5df451ab911421da96655fcc4d1e269ff6e2f Mon Sep 17 00:00:00 2001
   2 From: Mantas Pucka <mantas@8devices.com>
   3 Date: Tue, 23 Jan 2024 18:09:20 +0200
   4 Subject: [PATCH] phy: qcom-qmp-usb: fix serdes init sequence for IPQ6018
   5
   6 Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
   7 noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses
   8 separate serdes init sequence for IPQ6018. Since already existing IPQ9574
   9 serdes init sequence is identical, just reuse it and fix failing USB3 mode
  10 in IPQ6018.
  11
  12 Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
  13 Signed-off-by: Mantas Pucka <mantas@8devices.com>
  14 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  15 Link: https://lore.kernel.org/r/1706026160-17520-3-git-send-email-mantas@8devices.com
  16 Signed-off-by: Vinod Koul <vkoul@kernel.org>
  17 ---
  18  drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++++++++++++++++-
  19  1 file changed, 19 insertions(+), 1 deletion(-)
  20
  21 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
  22 +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
  23 @@ -233,6 +233,43 @@ static const struct qmp_phy_init_tbl ipq
  24         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
  25  };
  26
  27 +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
  28 +       QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
  29 +       QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
  30 +       QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
  31 +       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
  32 +       QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
  33 +       QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
  34 +       QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
  35 +       QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
  36 +       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
  37 +       QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
  38 +       /* PLL and Loop filter settings */
  39 +       QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
  40 +       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
  41 +       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
  42 +       QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
  43 +       QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
  44 +       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
  45 +       QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
  46 +       QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
  47 +       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
  48 +       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
  49 +       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
  50 +       QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
  51 +       QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
  52 +       QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
  53 +       QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
  54 +       /* SSC settings */
  55 +       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
  56 +       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
  57 +       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
  58 +       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
  59 +       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
  60 +       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
  61 +       QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
  62 +};
  63 +
  64  static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
  65         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
  66         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
  67 @@ -1591,6 +1628,26 @@ static const char * const qmp_phy_vreg_l
  68         "vdda-phy", "vdda-pll",
  69  };
  70
  71 +static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
  72 +       .lanes                  = 1,
  73 +
  74 +       .serdes_tbl             = ipq9574_usb3_serdes_tbl,
  75 +       .serdes_tbl_num         = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
  76 +       .tx_tbl                 = msm8996_usb3_tx_tbl,
  77 +       .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
  78 +       .rx_tbl                 = ipq8074_usb3_rx_tbl,
  79 +       .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
  80 +       .pcs_tbl                = ipq8074_usb3_pcs_tbl,
  81 +       .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
  82 +       .clk_list               = msm8996_phy_clk_l,
  83 +       .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
  84 +       .reset_list             = msm8996_usb3phy_reset_l,
  85 +       .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
  86 +       .vreg_list              = qmp_phy_vreg_l,
  87 +       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
  88 +       .regs                   = qmp_v3_usb3phy_regs_layout,
  89 +};
  90 +
  91  static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
  92         .lanes                  = 1,
  93
  94 @@ -2534,7 +2591,7 @@ static const struct of_device_id qmp_usb
  95                 .data = &msm8996_usb3phy_cfg,
  96         }, {
  97                 .compatible = "qcom,ipq6018-qmp-usb3-phy",
  98 -               .data = &ipq8074_usb3phy_cfg,
  99 +               .data = &ipq6018_usb3phy_cfg,
 100         }, {
 101                 .compatible = "qcom,sc7180-qmp-usb3-phy",
 102                 .data = &sc7180_usb3phy_cfg,