git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From bcb9ab4c2917e92114d2f4c2b1da97cdf15b471b Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Wed, 25 Jul 2018 10:37:46 +0200
   4 Subject: [PATCH] ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq
   5  support
   6
   7 This adds some operating points for cpu frequeny scaling
   8
   9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  10 Signed-off-by: John Crispin <john@phrozen.org>
  11 Signed-off-by: Andy Gross <andy.gross@linaro.org>
  12 ---
  13  arch/arm/boot/dts/qcom-ipq4019.dtsi | 58 ++++++++++++++---------------
  14  1 file changed, 30 insertions(+), 28 deletions(-)
  15
  16 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  17 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  18 @@ -59,14 +59,8 @@
  19                         reg = <0x0>;
  20                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  21                         clock-frequency = <0>;
  22 -                       operating-points = <
  23 -                               /* kHz  uV (fixed) */
  24 -                               48000   1100000
  25 -                               200000  1100000
  26 -                               500000  1100000
  27 -                               716000  1100000
  28 -                       >;
  29                         clock-latency = <256000>;
  30 +                       operating-points-v2 = <&cpu0_opp_table>;
  31                 };
  32
  33                 cpu@1 {
  34 @@ -79,14 +73,8 @@
  35                         reg = <0x1>;
  36                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  37                         clock-frequency = <0>;
  38 -                       operating-points = <
  39 -                               /* kHz  uV (fixed) */
  40 -                               48000   1100000
  41 -                               200000  1100000
  42 -                               500000  1100000
  43 -                               666000  1100000
  44 -                       >;
  45                         clock-latency = <256000>;
  46 +                       operating-points-v2 = <&cpu0_opp_table>;
  47                 };
  48
  49                 cpu@2 {
  50 @@ -99,14 +87,8 @@
  51                         reg = <0x2>;
  52                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  53                         clock-frequency = <0>;
  54 -                       operating-points = <
  55 -                               /* kHz  uV (fixed) */
  56 -                               48000   1100000
  57 -                               200000  1100000
  58 -                               500000  1100000
  59 -                               666000  1100000
  60 -                       >;
  61                         clock-latency = <256000>;
  62 +                       operating-points-v2 = <&cpu0_opp_table>;
  63                 };
  64
  65                 cpu@3 {
  66 @@ -119,14 +101,8 @@
  67                         reg = <0x3>;
  68                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  69                         clock-frequency = <0>;
  70 -                       operating-points = <
  71 -                               /* kHz  uV (fixed) */
  72 -                               48000   1100000
  73 -                               200000  1100000
  74 -                               500000  1100000
  75 -                               666000  1100000
  76 -                       >;
  77                         clock-latency = <256000>;
  78 +                       operating-points-v2 = <&cpu0_opp_table>;
  79                 };
  80
  81                 L2: l2-cache {
  82 @@ -136,6 +112,32 @@
  83                 };
  84         };
  85
  86 +       cpu0_opp_table: opp_table0 {
  87 +               compatible = "operating-points-v2";
  88 +               opp-shared;
  89 +
  90 +               opp-48000000 {
  91 +                       opp-hz = /bits/ 64 <48000000>;
  92 +                       opp-microvolt = <1100000>;
  93 +                       clock-latency-ns = <256000>;
  94 +               };
  95 +               opp-200000000 {
  96 +                       opp-hz = /bits/ 64 <200000000>;
  97 +                       opp-microvolt = <1100000>;
  98 +                       clock-latency-ns = <256000>;
  99 +               };
 100 +               opp-500000000 {
 101 +                       opp-hz = /bits/ 64 <500000000>;
 102 +                       opp-microvolt = <1100000>;
 103 +                       clock-latency-ns = <256000>;
 104 +               };
 105 +               opp-716000000 {
 106 +                       opp-hz = /bits/ 64 <716000000>;
 107 +                       opp-microvolt = <1100000>;
 108 +                       clock-latency-ns = <256000>;
 109 +               };
 110 +       };
 111 +
 112         pmu {
 113                 compatible = "arm,cortex-a7-pmu";
 114                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |