projects / openwrt / staging / stintel.git / blob
? search:


9abe293dee070a1de270b14dfcc036310c57c939
[openwrt/staging/stintel.git] /
1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Wed, 24 Mar 2021 02:30:53 +0100
3 Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for
4 initializing the PPE
5
6 The PPE (packet processing engine) is used to offload NAT/routed or even
7 bridged flows. This patch brings up the PPE and uses it to get a packet
8 hash. It also contains some functionality that will be used to bring up
9 flow offloading.
10
11 Signed-off-by: Felix Fietkau <nbd@nbd.name>
12 Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
13 ---
14 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.c
15 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.h
16 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
17 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_regs.h
18
19 --- a/drivers/net/ethernet/mediatek/Makefile
20 +++ b/drivers/net/ethernet/mediatek/Makefile
21 @@ -4,5 +4,5 @@
22 #
23
24 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
25 -mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
26 +mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o
27 obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o
28 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
29 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
30 @@ -2282,12 +2282,17 @@ static int mtk_open(struct net_device *d
31
32 /* we run 2 netdevs on the same dma ring so we only bring it up once */
33 if (!refcount_read(&eth->dma_refcnt)) {
34 - int err = mtk_start_dma(eth);
35 + u32 gdm_config = MTK_GDMA_TO_PDMA;
36 + int err;
37
38 + err = mtk_start_dma(eth);
39 if (err)
40 return err;
41
42 - mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
43 + if (eth->soc->offload_version && mtk_ppe_start(&eth->ppe) == 0)
44 + gdm_config = MTK_GDMA_TO_PPE;
45 +
46 + mtk_gdm_config(eth, gdm_config);
47
48 napi_enable(&eth->tx_napi);
49 napi_enable(&eth->rx_napi);
50 @@ -2354,6 +2359,9 @@ static int mtk_stop(struct net_device *d
51
52 mtk_dma_free(eth);
53
54 + if (eth->soc->offload_version)
55 + mtk_ppe_stop(&eth->ppe);
56 +
57 return 0;
58 }
59
60 @@ -3082,6 +3090,13 @@ static int mtk_probe(struct platform_dev
61 goto err_free_dev;
62 }
63
64 + if (eth->soc->offload_version) {
65 + err = mtk_ppe_init(&eth->ppe, eth->dev,
66 + eth->base + MTK_ETH_PPE_BASE, 2);
67 + if (err)
68 + goto err_free_dev;
69 + }
70 +
71 for (i = 0; i < MTK_MAX_DEVS; i++) {
72 if (!eth->netdev[i])
73 continue;
74 @@ -3156,6 +3171,7 @@ static const struct mtk_soc_data mt7621_
75 .hw_features = MTK_HW_FEATURES,
76 .required_clks = MT7621_CLKS_BITMAP,
77 .required_pctl = false,
78 + .offload_version = 2,
79 };
80
81 static const struct mtk_soc_data mt7622_data = {
82 @@ -3164,6 +3180,7 @@ static const struct mtk_soc_data mt7622_
83 .hw_features = MTK_HW_FEATURES,
84 .required_clks = MT7622_CLKS_BITMAP,
85 .required_pctl = false,
86 + .offload_version = 2,
87 };
88
89 static const struct mtk_soc_data mt7623_data = {
90 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
91 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
92 @@ -15,6 +15,7 @@
93 #include <linux/u64_stats_sync.h>
94 #include <linux/refcount.h>
95 #include <linux/phylink.h>
96 +#include "mtk_ppe.h"
97
98 #define MTK_QDMA_PAGE_SIZE 2048
99 #define MTK_MAX_RX_LENGTH 1536
100 @@ -86,6 +87,7 @@
101 #define MTK_GDMA_TCS_EN BIT(21)
102 #define MTK_GDMA_UCS_EN BIT(20)
103 #define MTK_GDMA_TO_PDMA 0x0
104 +#define MTK_GDMA_TO_PPE 0x4444
105 #define MTK_GDMA_DROP_ALL 0x7777
106
107 /* Unicast Filter MAC Address Register - Low */
108 @@ -315,6 +317,12 @@
109 #define RX_DMA_VID(_x) ((_x) & 0xfff)
110
111 /* QDMA descriptor rxd4 */
112 +#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
113 +#define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)
114 +#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
115 +#define MTK_RXD4_ALG GENMASK(31, 22)
116 +
117 +/* QDMA descriptor rxd4 */
118 #define RX_DMA_L4_VALID BIT(24)
119 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
120 #define RX_DMA_FPORT_SHIFT 19
121 @@ -819,6 +827,7 @@ struct mtk_soc_data {
122 u32 caps;
123 u32 required_clks;
124 bool required_pctl;
125 + u8 offload_version;
126 netdev_features_t hw_features;
127 };
128
129 @@ -918,6 +927,8 @@ struct mtk_eth {
130 u32 tx_int_status_reg;
131 u32 rx_dma_l4_valid;
132 int ip_align;
133 +
134 + struct mtk_ppe ppe;
135 };
136
137 /* struct mtk_mac - the structure that holds the info about the MACs of the
138 --- /dev/null
139 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
140 @@ -0,0 +1,511 @@
141 +// SPDX-License-Identifier: GPL-2.0-only
142 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
143 +
144 +#include <linux/kernel.h>
145 +#include <linux/jiffies.h>
146 +#include <linux/delay.h>
147 +#include <linux/io.h>
148 +#include <linux/etherdevice.h>
149 +#include <linux/platform_device.h>
150 +#include "mtk_ppe.h"
151 +#include "mtk_ppe_regs.h"
152 +
153 +static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)
154 +{
155 + writel(val, ppe->base + reg);
156 +}
157 +
158 +static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg)
159 +{
160 + return readl(ppe->base + reg);
161 +}
162 +
163 +static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set)
164 +{
165 + u32 val;
166 +
167 + val = ppe_r32(ppe, reg);
168 + val &= ~mask;
169 + val |= set;
170 + ppe_w32(ppe, reg, val);
171 +
172 + return val;
173 +}
174 +
175 +static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val)
176 +{
177 + return ppe_m32(ppe, reg, 0, val);
178 +}
179 +
180 +static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val)
181 +{
182 + return ppe_m32(ppe, reg, val, 0);
183 +}
184 +
185 +static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)
186 +{
187 + unsigned long timeout = jiffies + HZ;
188 +
189 + while (time_is_before_jiffies(timeout)) {
190 + if (!(ppe_r32(ppe, MTK_PPE_GLO_CFG) & MTK_PPE_GLO_CFG_BUSY))
191 + return 0;
192 +
193 + usleep_range(10, 20);
194 + }
195 +
196 + dev_err(ppe->dev, "PPE table busy");
197 +
198 + return -ETIMEDOUT;
199 +}
200 +
201 +static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
202 +{
203 + ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
204 + ppe_clear(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
205 +}
206 +
207 +static void mtk_ppe_cache_enable(struct mtk_ppe *ppe, bool enable)
208 +{
209 + mtk_ppe_cache_clear(ppe);
210 +
211 + ppe_m32(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_EN,
212 + enable * MTK_PPE_CACHE_CTL_EN);
213 +}
214 +
215 +static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e)
216 +{
217 + u32 hv1, hv2, hv3;
218 + u32 hash;
219 +
220 + switch (FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, e->ib1)) {
221 + case MTK_PPE_PKT_TYPE_BRIDGE:
222 + hv1 = e->bridge.src_mac_lo;
223 + hv1 ^= ((e->bridge.src_mac_hi & 0xffff) << 16);
224 + hv2 = e->bridge.src_mac_hi >> 16;
225 + hv2 ^= e->bridge.dest_mac_lo;
226 + hv3 = e->bridge.dest_mac_hi;
227 + break;
228 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
229 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
230 + hv1 = e->ipv4.orig.ports;
231 + hv2 = e->ipv4.orig.dest_ip;
232 + hv3 = e->ipv4.orig.src_ip;
233 + break;
234 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
235 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
236 + hv1 = e->ipv6.src_ip[3] ^ e->ipv6.dest_ip[3];
237 + hv1 ^= e->ipv6.ports;
238 +
239 + hv2 = e->ipv6.src_ip[2] ^ e->ipv6.dest_ip[2];
240 + hv2 ^= e->ipv6.dest_ip[0];
241 +
242 + hv3 = e->ipv6.src_ip[1] ^ e->ipv6.dest_ip[1];
243 + hv3 ^= e->ipv6.src_ip[0];
244 + break;
245 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
246 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
247 + default:
248 + WARN_ON_ONCE(1);
249 + return MTK_PPE_HASH_MASK;
250 + }
251 +
252 + hash = (hv1 & hv2) | ((~hv1) & hv3);
253 + hash = (hash >> 24) | ((hash & 0xffffff) << 8);
254 + hash ^= hv1 ^ hv2 ^ hv3;
255 + hash ^= hash >> 16;
256 + hash <<= 1;
257 + hash &= MTK_PPE_ENTRIES - 1;
258 +
259 + return hash;
260 +}
261 +
262 +static inline struct mtk_foe_mac_info *
263 +mtk_foe_entry_l2(struct mtk_foe_entry *entry)
264 +{
265 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
266 +
267 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)
268 + return &entry->ipv6.l2;
269 +
270 + return &entry->ipv4.l2;
271 +}
272 +
273 +static inline u32 *
274 +mtk_foe_entry_ib2(struct mtk_foe_entry *entry)
275 +{
276 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
277 +
278 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)
279 + return &entry->ipv6.ib2;
280 +
281 + return &entry->ipv4.ib2;
282 +}
283 +
284 +int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
285 + u8 pse_port, u8 *src_mac, u8 *dest_mac)
286 +{
287 + struct mtk_foe_mac_info *l2;
288 + u32 ports_pad, val;
289 +
290 + memset(entry, 0, sizeof(*entry));
291 +
292 + val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |
293 + FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE, type) |
294 + FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |
295 + MTK_FOE_IB1_BIND_TTL |
296 + MTK_FOE_IB1_BIND_CACHE;
297 + entry->ib1 = val;
298 +
299 + val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) |
300 + FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0x1f) |
301 + FIELD_PREP(MTK_FOE_IB2_DEST_PORT, pse_port);
302 +
303 + if (is_multicast_ether_addr(dest_mac))
304 + val |= MTK_FOE_IB2_MULTICAST;
305 +
306 + ports_pad = 0xa5a5a500 | (l4proto & 0xff);
307 + if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)
308 + entry->ipv4.orig.ports = ports_pad;
309 + if (type == MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)
310 + entry->ipv6.ports = ports_pad;
311 +
312 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {
313 + entry->ipv6.ib2 = val;
314 + l2 = &entry->ipv6.l2;
315 + } else {
316 + entry->ipv4.ib2 = val;
317 + l2 = &entry->ipv4.l2;
318 + }
319 +
320 + l2->dest_mac_hi = get_unaligned_be32(dest_mac);
321 + l2->dest_mac_lo = get_unaligned_be16(dest_mac + 4);
322 + l2->src_mac_hi = get_unaligned_be32(src_mac);
323 + l2->src_mac_lo = get_unaligned_be16(src_mac + 4);
324 +
325 + if (type >= MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)
326 + l2->etype = ETH_P_IPV6;
327 + else
328 + l2->etype = ETH_P_IP;
329 +
330 + return 0;
331 +}
332 +
333 +int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port)
334 +{
335 + u32 *ib2 = mtk_foe_entry_ib2(entry);
336 + u32 val;
337 +
338 + val = *ib2;
339 + val &= ~MTK_FOE_IB2_DEST_PORT;
340 + val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT, port);
341 + *ib2 = val;
342 +
343 + return 0;
344 +}
345 +
346 +int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool egress,
347 + __be32 src_addr, __be16 src_port,
348 + __be32 dest_addr, __be16 dest_port)
349 +{
350 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
351 + struct mtk_ipv4_tuple *t;
352 +
353 + switch (type) {
354 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
355 + if (egress) {
356 + t = &entry->ipv4.new;
357 + break;
358 + }
359 + fallthrough;
360 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
361 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
362 + t = &entry->ipv4.orig;
363 + break;
364 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
365 + entry->ipv6_6rd.tunnel_src_ip = be32_to_cpu(src_addr);
366 + entry->ipv6_6rd.tunnel_dest_ip = be32_to_cpu(dest_addr);
367 + return 0;
368 + default:
369 + WARN_ON_ONCE(1);
370 + return -EINVAL;
371 + }
372 +
373 + t->src_ip = be32_to_cpu(src_addr);
374 + t->dest_ip = be32_to_cpu(dest_addr);
375 +
376 + if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)
377 + return 0;
378 +
379 + t->src_port = be16_to_cpu(src_port);
380 + t->dest_port = be16_to_cpu(dest_port);
381 +
382 + return 0;
383 +}
384 +
385 +int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,
386 + __be32 *src_addr, __be16 src_port,
387 + __be32 *dest_addr, __be16 dest_port)
388 +{
389 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
390 + u32 *src, *dest;
391 + int i;
392 +
393 + switch (type) {
394 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
395 + src = entry->dslite.tunnel_src_ip;
396 + dest = entry->dslite.tunnel_dest_ip;
397 + break;
398 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
399 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
400 + entry->ipv6.src_port = be16_to_cpu(src_port);
401 + entry->ipv6.dest_port = be16_to_cpu(dest_port);
402 + fallthrough;
403 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
404 + src = entry->ipv6.src_ip;
405 + dest = entry->ipv6.dest_ip;
406 + break;
407 + default:
408 + WARN_ON_ONCE(1);
409 + return -EINVAL;
410 + };
411 +
412 + for (i = 0; i < 4; i++)
413 + src[i] = be32_to_cpu(src_addr[i]);
414 + for (i = 0; i < 4; i++)
415 + dest[i] = be32_to_cpu(dest_addr[i]);
416 +
417 + return 0;
418 +}
419 +
420 +int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port)
421 +{
422 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
423 +
424 + l2->etype = BIT(port);
425 +
426 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER))
427 + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
428 + else
429 + l2->etype |= BIT(8);
430 +
431 + entry->ib1 &= ~MTK_FOE_IB1_BIND_VLAN_TAG;
432 +
433 + return 0;
434 +}
435 +
436 +int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid)
437 +{
438 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
439 +
440 + switch (FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, entry->ib1)) {
441 + case 0:
442 + entry->ib1 |= MTK_FOE_IB1_BIND_VLAN_TAG |
443 + FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
444 + l2->vlan1 = vid;
445 + return 0;
446 + case 1:
447 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG)) {
448 + l2->vlan1 = vid;
449 + l2->etype |= BIT(8);
450 + } else {
451 + l2->vlan2 = vid;
452 + entry->ib1 += FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
453 + }
454 + return 0;
455 + default:
456 + return -ENOSPC;
457 + }
458 +}
459 +
460 +int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid)
461 +{
462 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
463 +
464 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER) ||
465 + (entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG))
466 + l2->etype = ETH_P_PPP_SES;
467 +
468 + entry->ib1 |= MTK_FOE_IB1_BIND_PPPOE;
469 + l2->pppoe_id = sid;
470 +
471 + return 0;
472 +}
473 +
474 +static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry)
475 +{
476 + return !(entry->ib1 & MTK_FOE_IB1_STATIC) &&
477 + FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1) != MTK_FOE_STATE_BIND;
478 +}
479 +
480 +int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
481 + u16 timestamp)
482 +{
483 + struct mtk_foe_entry *hwe;
484 + u32 hash;
485 +
486 + timestamp &= MTK_FOE_IB1_BIND_TIMESTAMP;
487 + entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP;
488 + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP, timestamp);
489 +
490 + hash = mtk_ppe_hash_entry(entry);
491 + hwe = &ppe->foe_table[hash];
492 + if (!mtk_foe_entry_usable(hwe)) {
493 + hwe++;
494 + hash++;
495 +
496 + if (!mtk_foe_entry_usable(hwe))
497 + return -ENOSPC;
498 + }
499 +
500 + memcpy(&hwe->data, &entry->data, sizeof(hwe->data));
501 + wmb();
502 + hwe->ib1 = entry->ib1;
503 +
504 + dma_wmb();
505 +
506 + mtk_ppe_cache_clear(ppe);
507 +
508 + return hash;
509 +}
510 +
511 +int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,
512 + int version)
513 +{
514 + struct mtk_foe_entry *foe;
515 +
516 + /* need to allocate a separate device, since it PPE DMA access is
517 + * not coherent.
518 + */
519 + ppe->base = base;
520 + ppe->dev = dev;
521 + ppe->version = version;
522 +
523 + foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe),
524 + &ppe->foe_phys, GFP_KERNEL);
525 + if (!foe)
526 + return -ENOMEM;
527 +
528 + ppe->foe_table = foe;
529 +
530 + mtk_ppe_debugfs_init(ppe);
531 +
532 + return 0;
533 +}
534 +
535 +static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe)
536 +{
537 + static const u8 skip[] = { 12, 25, 38, 51, 76, 89, 102 };
538 + int i, k;
539 +
540 + memset(ppe->foe_table, 0, MTK_PPE_ENTRIES * sizeof(ppe->foe_table));
541 +
542 + if (!IS_ENABLED(CONFIG_SOC_MT7621))
543 + return;
544 +
545 + /* skip all entries that cross the 1024 byte boundary */
546 + for (i = 0; i < MTK_PPE_ENTRIES; i += 128)
547 + for (k = 0; k < ARRAY_SIZE(skip); k++)
548 + ppe->foe_table[i + skip[k]].ib1 |= MTK_FOE_IB1_STATIC;
549 +}
550 +
551 +int mtk_ppe_start(struct mtk_ppe *ppe)
552 +{
553 + u32 val;
554 +
555 + mtk_ppe_init_foe_table(ppe);
556 + ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
557 +
558 + val = MTK_PPE_TB_CFG_ENTRY_80B |
559 + MTK_PPE_TB_CFG_AGE_NON_L4 |
560 + MTK_PPE_TB_CFG_AGE_UNBIND |
561 + MTK_PPE_TB_CFG_AGE_TCP |
562 + MTK_PPE_TB_CFG_AGE_UDP |
563 + MTK_PPE_TB_CFG_AGE_TCP_FIN |
564 + FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS,
565 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD) |
566 + FIELD_PREP(MTK_PPE_TB_CFG_KEEPALIVE,
567 + MTK_PPE_KEEPALIVE_DISABLE) |
568 + FIELD_PREP(MTK_PPE_TB_CFG_HASH_MODE, 1) |
569 + FIELD_PREP(MTK_PPE_TB_CFG_SCAN_MODE,
570 + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
571 + FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
572 + MTK_PPE_ENTRIES_SHIFT);
573 + ppe_w32(ppe, MTK_PPE_TB_CFG, val);
574 +
575 + ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,
576 + MTK_PPE_IP_PROTO_CHK_IPV4 | MTK_PPE_IP_PROTO_CHK_IPV6);
577 +
578 + mtk_ppe_cache_enable(ppe, true);
579 +
580 + val = MTK_PPE_FLOW_CFG_IP4_TCP_FRAG |
581 + MTK_PPE_FLOW_CFG_IP4_UDP_FRAG |
582 + MTK_PPE_FLOW_CFG_IP6_3T_ROUTE |
583 + MTK_PPE_FLOW_CFG_IP6_5T_ROUTE |
584 + MTK_PPE_FLOW_CFG_IP6_6RD |
585 + MTK_PPE_FLOW_CFG_IP4_NAT |
586 + MTK_PPE_FLOW_CFG_IP4_NAPT |
587 + MTK_PPE_FLOW_CFG_IP4_DSLITE |
588 + MTK_PPE_FLOW_CFG_L2_BRIDGE |
589 + MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;
590 + ppe_w32(ppe, MTK_PPE_FLOW_CFG, val);
591 +
592 + val = FIELD_PREP(MTK_PPE_UNBIND_AGE_MIN_PACKETS, 1000) |
593 + FIELD_PREP(MTK_PPE_UNBIND_AGE_DELTA, 3);
594 + ppe_w32(ppe, MTK_PPE_UNBIND_AGE, val);
595 +
596 + val = FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_UDP, 12) |
597 + FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_NON_L4, 1);
598 + ppe_w32(ppe, MTK_PPE_BIND_AGE0, val);
599 +
600 + val = FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP_FIN, 1) |
601 + FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP, 7);
602 + ppe_w32(ppe, MTK_PPE_BIND_AGE1, val);
603 +
604 + val = MTK_PPE_BIND_LIMIT0_QUARTER | MTK_PPE_BIND_LIMIT0_HALF;
605 + ppe_w32(ppe, MTK_PPE_BIND_LIMIT0, val);
606 +
607 + val = MTK_PPE_BIND_LIMIT1_FULL |
608 + FIELD_PREP(MTK_PPE_BIND_LIMIT1_NON_L4, 1);
609 + ppe_w32(ppe, MTK_PPE_BIND_LIMIT1, val);
610 +
611 + val = FIELD_PREP(MTK_PPE_BIND_RATE_BIND, 30) |
612 + FIELD_PREP(MTK_PPE_BIND_RATE_PREBIND, 1);
613 + ppe_w32(ppe, MTK_PPE_BIND_RATE, val);
614 +
615 + /* enable PPE */
616 + val = MTK_PPE_GLO_CFG_EN |
617 + MTK_PPE_GLO_CFG_IP4_L4_CS_DROP |
618 + MTK_PPE_GLO_CFG_IP4_CS_DROP |
619 + MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE;
620 + ppe_w32(ppe, MTK_PPE_GLO_CFG, val);
621 +
622 + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
623 +
624 + return 0;
625 +}
626 +
627 +int mtk_ppe_stop(struct mtk_ppe *ppe)
628 +{
629 + u32 val;
630 + int i;
631 +
632 + for (i = 0; i < MTK_PPE_ENTRIES; i++)
633 + ppe->foe_table[i].ib1 = FIELD_PREP(MTK_FOE_IB1_STATE,
634 + MTK_FOE_STATE_INVALID);
635 +
636 + mtk_ppe_cache_enable(ppe, false);
637 +
638 + /* disable offload engine */
639 + ppe_clear(ppe, MTK_PPE_GLO_CFG, MTK_PPE_GLO_CFG_EN);
640 + ppe_w32(ppe, MTK_PPE_FLOW_CFG, 0);
641 +
642 + /* disable aging */
643 + val = MTK_PPE_TB_CFG_AGE_NON_L4 |
644 + MTK_PPE_TB_CFG_AGE_UNBIND |
645 + MTK_PPE_TB_CFG_AGE_TCP |
646 + MTK_PPE_TB_CFG_AGE_UDP |
647 + MTK_PPE_TB_CFG_AGE_TCP_FIN;
648 + ppe_clear(ppe, MTK_PPE_TB_CFG, val);
649 +
650 + return mtk_ppe_wait_busy(ppe);
651 +}
652 --- /dev/null
653 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
654 @@ -0,0 +1,287 @@
655 +// SPDX-License-Identifier: GPL-2.0-only
656 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
657 +
658 +#ifndef __MTK_PPE_H
659 +#define __MTK_PPE_H
660 +
661 +#include <linux/kernel.h>
662 +#include <linux/bitfield.h>
663 +
664 +#define MTK_ETH_PPE_BASE 0xc00
665 +
666 +#define MTK_PPE_ENTRIES_SHIFT 3
667 +#define MTK_PPE_ENTRIES (1024 << MTK_PPE_ENTRIES_SHIFT)
668 +#define MTK_PPE_HASH_MASK (MTK_PPE_ENTRIES - 1)
669 +
670 +#define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0)
671 +#define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8)
672 +#define MTK_FOE_IB1_UNBIND_PREBIND BIT(24)
673 +
674 +#define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0)
675 +#define MTK_FOE_IB1_BIND_KEEPALIVE BIT(15)
676 +#define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(18, 16)
677 +#define MTK_FOE_IB1_BIND_PPPOE BIT(19)
678 +#define MTK_FOE_IB1_BIND_VLAN_TAG BIT(20)
679 +#define MTK_FOE_IB1_BIND_PKT_SAMPLE BIT(21)
680 +#define MTK_FOE_IB1_BIND_CACHE BIT(22)
681 +#define MTK_FOE_IB1_BIND_TUNNEL_DECAP BIT(23)
682 +#define MTK_FOE_IB1_BIND_TTL BIT(24)
683 +
684 +#define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 25)
685 +#define MTK_FOE_IB1_STATE GENMASK(29, 28)
686 +#define MTK_FOE_IB1_UDP BIT(30)
687 +#define MTK_FOE_IB1_STATIC BIT(31)
688 +
689 +enum {
690 + MTK_PPE_PKT_TYPE_IPV4_HNAPT = 0,
691 + MTK_PPE_PKT_TYPE_IPV4_ROUTE = 1,
692 + MTK_PPE_PKT_TYPE_BRIDGE = 2,
693 + MTK_PPE_PKT_TYPE_IPV4_DSLITE = 3,
694 + MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,
695 + MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,
696 + MTK_PPE_PKT_TYPE_IPV6_6RD = 7,
697 +};
698 +
699 +#define MTK_FOE_IB2_QID GENMASK(3, 0)
700 +#define MTK_FOE_IB2_PSE_QOS BIT(4)
701 +#define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5)
702 +#define MTK_FOE_IB2_MULTICAST BIT(8)
703 +
704 +#define MTK_FOE_IB2_WHNAT_QID2 GENMASK(13, 12)
705 +#define MTK_FOE_IB2_WHNAT_DEVIDX BIT(16)
706 +#define MTK_FOE_IB2_WHNAT_NAT BIT(17)
707 +
708 +#define MTK_FOE_IB2_PORT_MG GENMASK(17, 12)
709 +
710 +#define MTK_FOE_IB2_PORT_AG GENMASK(23, 18)
711 +
712 +#define MTK_FOE_IB2_DSCP GENMASK(31, 24)
713 +
714 +#define MTK_FOE_VLAN2_WHNAT_BSS GEMMASK(5, 0)
715 +#define MTK_FOE_VLAN2_WHNAT_WCID GENMASK(13, 6)
716 +#define MTK_FOE_VLAN2_WHNAT_RING GENMASK(15, 14)
717 +
718 +enum {
719 + MTK_FOE_STATE_INVALID,
720 + MTK_FOE_STATE_UNBIND,
721 + MTK_FOE_STATE_BIND,
722 + MTK_FOE_STATE_FIN
723 +};
724 +
725 +struct mtk_foe_mac_info {
726 + u16 vlan1;
727 + u16 etype;
728 +
729 + u32 dest_mac_hi;
730 +
731 + u16 vlan2;
732 + u16 dest_mac_lo;
733 +
734 + u32 src_mac_hi;
735 +
736 + u16 pppoe_id;
737 + u16 src_mac_lo;
738 +};
739 +
740 +struct mtk_foe_bridge {
741 + u32 dest_mac_hi;
742 +
743 + u16 src_mac_lo;
744 + u16 dest_mac_lo;
745 +
746 + u32 src_mac_hi;
747 +
748 + u32 ib2;
749 +
750 + u32 _rsv[5];
751 +
752 + u32 udf_tsid;
753 + struct mtk_foe_mac_info l2;
754 +};
755 +
756 +struct mtk_ipv4_tuple {
757 + u32 src_ip;
758 + u32 dest_ip;
759 + union {
760 + struct {
761 + u16 dest_port;
762 + u16 src_port;
763 + };
764 + struct {
765 + u8 protocol;
766 + u8 _pad[3]; /* fill with 0xa5a5a5 */
767 + };
768 + u32 ports;
769 + };
770 +};
771 +
772 +struct mtk_foe_ipv4 {
773 + struct mtk_ipv4_tuple orig;
774 +
775 + u32 ib2;
776 +
777 + struct mtk_ipv4_tuple new;
778 +
779 + u16 timestamp;
780 + u16 _rsv0[3];
781 +
782 + u32 udf_tsid;
783 +
784 + struct mtk_foe_mac_info l2;
785 +};
786 +
787 +struct mtk_foe_ipv4_dslite {
788 + struct mtk_ipv4_tuple ip4;
789 +
790 + u32 tunnel_src_ip[4];
791 + u32 tunnel_dest_ip[4];
792 +
793 + u8 flow_label[3];
794 + u8 priority;
795 +
796 + u32 udf_tsid;
797 +
798 + u32 ib2;
799 +
800 + struct mtk_foe_mac_info l2;
801 +};
802 +
803 +struct mtk_foe_ipv6 {
804 + u32 src_ip[4];
805 + u32 dest_ip[4];
806 +
807 + union {
808 + struct {
809 + u8 protocol;
810 + u8 _pad[3]; /* fill with 0xa5a5a5 */
811 + }; /* 3-tuple */
812 + struct {
813 + u16 dest_port;
814 + u16 src_port;
815 + }; /* 5-tuple */
816 + u32 ports;
817 + };
818 +
819 + u32 _rsv[3];
820 +
821 + u32 udf;
822 +
823 + u32 ib2;
824 + struct mtk_foe_mac_info l2;
825 +};
826 +
827 +struct mtk_foe_ipv6_6rd {
828 + u32 src_ip[4];
829 + u32 dest_ip[4];
830 + u16 dest_port;
831 + u16 src_port;
832 +
833 + u32 tunnel_src_ip;
834 + u32 tunnel_dest_ip;
835 +
836 + u16 hdr_csum;
837 + u8 dscp;
838 + u8 ttl;
839 +
840 + u8 flag;
841 + u8 pad;
842 + u8 per_flow_6rd_id;
843 + u8 pad2;
844 +
845 + u32 ib2;
846 + struct mtk_foe_mac_info l2;
847 +};
848 +
849 +struct mtk_foe_entry {
850 + u32 ib1;
851 +
852 + union {
853 + struct mtk_foe_bridge bridge;
854 + struct mtk_foe_ipv4 ipv4;
855 + struct mtk_foe_ipv4_dslite dslite;
856 + struct mtk_foe_ipv6 ipv6;
857 + struct mtk_foe_ipv6_6rd ipv6_6rd;
858 + u32 data[19];
859 + };
860 +};
861 +
862 +enum {
863 + MTK_PPE_CPU_REASON_TTL_EXCEEDED = 0x02,
864 + MTK_PPE_CPU_REASON_OPTION_HEADER = 0x03,
865 + MTK_PPE_CPU_REASON_NO_FLOW = 0x07,
866 + MTK_PPE_CPU_REASON_IPV4_FRAG = 0x08,
867 + MTK_PPE_CPU_REASON_IPV4_DSLITE_FRAG = 0x09,
868 + MTK_PPE_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a,
869 + MTK_PPE_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b,
870 + MTK_PPE_CPU_REASON_TCP_FIN_SYN_RST = 0x0c,
871 + MTK_PPE_CPU_REASON_UN_HIT = 0x0d,
872 + MTK_PPE_CPU_REASON_HIT_UNBIND = 0x0e,
873 + MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
874 + MTK_PPE_CPU_REASON_HIT_BIND_TCP_FIN = 0x10,
875 + MTK_PPE_CPU_REASON_HIT_TTL_1 = 0x11,
876 + MTK_PPE_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12,
877 + MTK_PPE_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13,
878 + MTK_PPE_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14,
879 + MTK_PPE_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15,
880 + MTK_PPE_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16,
881 + MTK_PPE_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17,
882 + MTK_PPE_CPU_REASON_MULTICAST_TO_CPU = 0x18,
883 + MTK_PPE_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19,
884 + MTK_PPE_CPU_REASON_HIT_PRE_BIND = 0x1a,
885 + MTK_PPE_CPU_REASON_PACKET_SAMPLING = 0x1b,
886 + MTK_PPE_CPU_REASON_EXCEED_MTU = 0x1c,
887 + MTK_PPE_CPU_REASON_PPE_BYPASS = 0x1e,
888 + MTK_PPE_CPU_REASON_INVALID = 0x1f,
889 +};
890 +
891 +struct mtk_ppe {
892 + struct device *dev;
893 + void __iomem *base;
894 + int version;
895 +
896 + struct mtk_foe_entry *foe_table;
897 + dma_addr_t foe_phys;
898 +
899 + void *acct_table;
900 +};
901 +
902 +int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,
903 + int version);
904 +int mtk_ppe_start(struct mtk_ppe *ppe);
905 +int mtk_ppe_stop(struct mtk_ppe *ppe);
906 +
907 +static inline void
908 +mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash)
909 +{
910 + ppe->foe_table[hash].ib1 = 0;
911 + dma_wmb();
912 +}
913 +
914 +static inline int
915 +mtk_foe_entry_timestamp(struct mtk_ppe *ppe, u16 hash)
916 +{
917 + u32 ib1 = READ_ONCE(ppe->foe_table[hash].ib1);
918 +
919 + if (FIELD_GET(MTK_FOE_IB1_STATE, ib1) != MTK_FOE_STATE_BIND)
920 + return -1;
921 +
922 + return FIELD_GET(MTK_FOE_IB1_BIND_TIMESTAMP, ib1);
923 +}
924 +
925 +int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
926 + u8 pse_port, u8 *src_mac, u8 *dest_mac);
927 +int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port);
928 +int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool orig,
929 + __be32 src_addr, __be16 src_port,
930 + __be32 dest_addr, __be16 dest_port);
931 +int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,
932 + __be32 *src_addr, __be16 src_port,
933 + __be32 *dest_addr, __be16 dest_port);
934 +int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port);
935 +int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid);
936 +int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);
937 +int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
938 + u16 timestamp);
939 +int mtk_ppe_debugfs_init(struct mtk_ppe *ppe);
940 +
941 +#endif
942 --- /dev/null
943 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
944 @@ -0,0 +1,217 @@
945 +// SPDX-License-Identifier: GPL-2.0-only
946 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
947 +
948 +#include <linux/kernel.h>
949 +#include <linux/debugfs.h>
950 +#include "mtk_eth_soc.h"
951 +
952 +struct mtk_flow_addr_info
953 +{
954 + void *src, *dest;
955 + u16 *src_port, *dest_port;
956 + bool ipv6;
957 +};
958 +
959 +static const char *mtk_foe_entry_state_str(int state)
960 +{
961 + static const char * const state_str[] = {
962 + [MTK_FOE_STATE_INVALID] = "INV",
963 + [MTK_FOE_STATE_UNBIND] = "UNB",
964 + [MTK_FOE_STATE_BIND] = "BND",
965 + [MTK_FOE_STATE_FIN] = "FIN",
966 + };
967 +
968 + if (state >= ARRAY_SIZE(state_str) || !state_str[state])
969 + return "UNK";
970 +
971 + return state_str[state];
972 +}
973 +
974 +static const char *mtk_foe_pkt_type_str(int type)
975 +{
976 + static const char * const type_str[] = {
977 + [MTK_PPE_PKT_TYPE_IPV4_HNAPT] = "IPv4 5T",
978 + [MTK_PPE_PKT_TYPE_IPV4_ROUTE] = "IPv4 3T",
979 + [MTK_PPE_PKT_TYPE_BRIDGE] = "L2",
980 + [MTK_PPE_PKT_TYPE_IPV4_DSLITE] = "DS-LITE",
981 + [MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T] = "IPv6 3T",
982 + [MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T] = "IPv6 5T",
983 + [MTK_PPE_PKT_TYPE_IPV6_6RD] = "6RD",
984 + };
985 +
986 + if (type >= ARRAY_SIZE(type_str) || !type_str[type])
987 + return "UNKNOWN";
988 +
989 + return type_str[type];
990 +}
991 +
992 +static void
993 +mtk_print_addr(struct seq_file *m, u32 *addr, bool ipv6)
994 +{
995 + u32 n_addr[4];
996 + int i;
997 +
998 + if (!ipv6) {
999 + seq_printf(m, "%pI4h", addr);
1000 + return;
1001 + }
1002 +
1003 + for (i = 0; i < ARRAY_SIZE(n_addr); i++)
1004 + n_addr[i] = htonl(addr[i]);
1005 + seq_printf(m, "%pI6", n_addr);
1006 +}
1007 +
1008 +static void
1009 +mtk_print_addr_info(struct seq_file *m, struct mtk_flow_addr_info *ai)
1010 +{
1011 + mtk_print_addr(m, ai->src, ai->ipv6);
1012 + if (ai->src_port)
1013 + seq_printf(m, ":%d", *ai->src_port);
1014 + seq_printf(m, "->");
1015 + mtk_print_addr(m, ai->dest, ai->ipv6);
1016 + if (ai->dest_port)
1017 + seq_printf(m, ":%d", *ai->dest_port);
1018 +}
1019 +
1020 +static int
1021 +mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private, bool bind)
1022 +{
1023 + struct mtk_ppe *ppe = m->private;
1024 + int i, count;
1025 +
1026 + for (i = 0, count = 0; i < MTK_PPE_ENTRIES; i++) {
1027 + struct mtk_foe_entry *entry = &ppe->foe_table[i];
1028 + struct mtk_foe_mac_info *l2;
1029 + struct mtk_flow_addr_info ai = {};
1030 + unsigned char h_source[ETH_ALEN];
1031 + unsigned char h_dest[ETH_ALEN];
1032 + int type, state;
1033 + u32 ib2;
1034 +
1035 +
1036 + state = FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1);
1037 + if (!state)
1038 + continue;
1039 +
1040 + if (bind && state != MTK_FOE_STATE_BIND)
1041 + continue;
1042 +
1043 + type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
1044 + seq_printf(m, "%05x %s %7s", i,
1045 + mtk_foe_entry_state_str(state),
1046 + mtk_foe_pkt_type_str(type));
1047 +
1048 + switch (type) {
1049 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
1050 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
1051 + ai.src_port = &entry->ipv4.orig.src_port;
1052 + ai.dest_port = &entry->ipv4.orig.dest_port;
1053 + fallthrough;
1054 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
1055 + ai.src = &entry->ipv4.orig.src_ip;
1056 + ai.dest = &entry->ipv4.orig.dest_ip;
1057 + break;
1058 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
1059 + ai.src_port = &entry->ipv6.src_port;
1060 + ai.dest_port = &entry->ipv6.dest_port;
1061 + fallthrough;
1062 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
1063 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
1064 + ai.src = &entry->ipv6.src_ip;
1065 + ai.dest = &entry->ipv6.dest_ip;
1066 + ai.ipv6 = true;
1067 + break;
1068 + }
1069 +
1070 + seq_printf(m, " orig=");
1071 + mtk_print_addr_info(m, &ai);
1072 +
1073 + switch (type) {
1074 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
1075 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
1076 + ai.src_port = &entry->ipv4.new.src_port;
1077 + ai.dest_port = &entry->ipv4.new.dest_port;
1078 + fallthrough;
1079 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
1080 + ai.src = &entry->ipv4.new.src_ip;
1081 + ai.dest = &entry->ipv4.new.dest_ip;
1082 + seq_printf(m, " new=");
1083 + mtk_print_addr_info(m, &ai);
1084 + break;
1085 + }
1086 +
1087 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {
1088 + l2 = &entry->ipv6.l2;
1089 + ib2 = entry->ipv6.ib2;
1090 + } else {
1091 + l2 = &entry->ipv4.l2;
1092 + ib2 = entry->ipv4.ib2;
1093 + }
1094 +
1095 + *((__be32 *)h_source) = htonl(l2->src_mac_hi);
1096 + *((__be16 *)&h_source[4]) = htons(l2->src_mac_lo);
1097 + *((__be32 *)h_dest) = htonl(l2->dest_mac_hi);
1098 + *((__be16 *)&h_dest[4]) = htons(l2->dest_mac_lo);
1099 +
1100 + seq_printf(m, " eth=%pM->%pM etype=%04x"
1101 + " vlan=%d,%d ib1=%08x ib2=%08x\n",
1102 + h_source, h_dest, ntohs(l2->etype),
1103 + l2->vlan1, l2->vlan2, entry->ib1, ib2);
1104 + }
1105 +
1106 + return 0;
1107 +}
1108 +
1109 +static int
1110 +mtk_ppe_debugfs_foe_show_all(struct seq_file *m, void *private)
1111 +{
1112 + return mtk_ppe_debugfs_foe_show(m, private, false);
1113 +}
1114 +
1115 +static int
1116 +mtk_ppe_debugfs_foe_show_bind(struct seq_file *m, void *private)
1117 +{
1118 + return mtk_ppe_debugfs_foe_show(m, private, true);
1119 +}
1120 +
1121 +static int
1122 +mtk_ppe_debugfs_foe_open_all(struct inode *inode, struct file *file)
1123 +{
1124 + return single_open(file, mtk_ppe_debugfs_foe_show_all,
1125 + inode->i_private);
1126 +}
1127 +
1128 +static int
1129 +mtk_ppe_debugfs_foe_open_bind(struct inode *inode, struct file *file)
1130 +{
1131 + return single_open(file, mtk_ppe_debugfs_foe_show_bind,
1132 + inode->i_private);
1133 +}
1134 +
1135 +int mtk_ppe_debugfs_init(struct mtk_ppe *ppe)
1136 +{
1137 + static const struct file_operations fops_all = {
1138 + .open = mtk_ppe_debugfs_foe_open_all,
1139 + .read = seq_read,
1140 + .llseek = seq_lseek,
1141 + .release = single_release,
1142 + };
1143 +
1144 + static const struct file_operations fops_bind = {
1145 + .open = mtk_ppe_debugfs_foe_open_bind,
1146 + .read = seq_read,
1147 + .llseek = seq_lseek,
1148 + .release = single_release,
1149 + };
1150 +
1151 + struct dentry *root;
1152 +
1153 + root = debugfs_create_dir("mtk_ppe", NULL);
1154 + if (!root)
1155 + return -ENOMEM;
1156 +
1157 + debugfs_create_file("entries", S_IRUGO, root, ppe, &fops_all);
1158 + debugfs_create_file("bind", S_IRUGO, root, ppe, &fops_bind);
1159 +
1160 + return 0;
1161 +}
1162 --- /dev/null
1163 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
1164 @@ -0,0 +1,144 @@
1165 +// SPDX-License-Identifier: GPL-2.0-only
1166 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
1167 +
1168 +#ifndef __MTK_PPE_REGS_H
1169 +#define __MTK_PPE_REGS_H
1170 +
1171 +#define MTK_PPE_GLO_CFG 0x200
1172 +#define MTK_PPE_GLO_CFG_EN BIT(0)
1173 +#define MTK_PPE_GLO_CFG_TSID_EN BIT(1)
1174 +#define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2)
1175 +#define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3)
1176 +#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
1177 +#define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5)
1178 +#define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6)
1179 +#define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7)
1180 +#define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8)
1181 +#define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE BIT(9)
1182 +#define MTK_PPE_GLO_CFG_UDP_LITE_EN BIT(10)
1183 +#define MTK_PPE_GLO_CFG_UDP_LEN_DROP BIT(11)
1184 +#define MTK_PPE_GLO_CFG_MCAST_ENTRIES GNEMASK(13, 12)
1185 +#define MTK_PPE_GLO_CFG_BUSY BIT(31)
1186 +
1187 +#define MTK_PPE_FLOW_CFG 0x204
1188 +#define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG BIT(6)
1189 +#define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG BIT(7)
1190 +#define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE BIT(8)
1191 +#define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE BIT(9)
1192 +#define MTK_PPE_FLOW_CFG_IP6_6RD BIT(10)
1193 +#define MTK_PPE_FLOW_CFG_IP4_NAT BIT(12)
1194 +#define MTK_PPE_FLOW_CFG_IP4_NAPT BIT(13)
1195 +#define MTK_PPE_FLOW_CFG_IP4_DSLITE BIT(14)
1196 +#define MTK_PPE_FLOW_CFG_L2_BRIDGE BIT(15)
1197 +#define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST BIT(16)
1198 +#define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG BIT(17)
1199 +#define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL BIT(18)
1200 +#define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY BIT(19)
1201 +#define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY BIT(20)
1202 +
1203 +#define MTK_PPE_IP_PROTO_CHK 0x208
1204 +#define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
1205 +#define MTK_PPE_IP_PROTO_CHK_IPV6 GENMASK(31, 16)
1206 +
1207 +#define MTK_PPE_TB_CFG 0x21c
1208 +#define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
1209 +#define MTK_PPE_TB_CFG_ENTRY_80B BIT(3)
1210 +#define MTK_PPE_TB_CFG_SEARCH_MISS GENMASK(5, 4)
1211 +#define MTK_PPE_TB_CFG_AGE_PREBIND BIT(6)
1212 +#define MTK_PPE_TB_CFG_AGE_NON_L4 BIT(7)
1213 +#define MTK_PPE_TB_CFG_AGE_UNBIND BIT(8)
1214 +#define MTK_PPE_TB_CFG_AGE_TCP BIT(9)
1215 +#define MTK_PPE_TB_CFG_AGE_UDP BIT(10)
1216 +#define MTK_PPE_TB_CFG_AGE_TCP_FIN BIT(11)
1217 +#define MTK_PPE_TB_CFG_KEEPALIVE GENMASK(13, 12)
1218 +#define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14)
1219 +#define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16)
1220 +#define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18)
1221 +
1222 +enum {
1223 + MTK_PPE_SCAN_MODE_DISABLED,
1224 + MTK_PPE_SCAN_MODE_CHECK_AGE,
1225 + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE,
1226 +};
1227 +
1228 +enum {
1229 + MTK_PPE_KEEPALIVE_DISABLE,
1230 + MTK_PPE_KEEPALIVE_UNICAST_CPU,
1231 + MTK_PPE_KEEPALIVE_DUP_CPU = 3,
1232 +};
1233 +
1234 +enum {
1235 + MTK_PPE_SEARCH_MISS_ACTION_DROP,
1236 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD = 2,
1237 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD = 3,
1238 +};
1239 +
1240 +#define MTK_PPE_TB_BASE 0x220
1241 +
1242 +#define MTK_PPE_TB_USED 0x224
1243 +#define MTK_PPE_TB_USED_NUM GENMASK(13, 0)
1244 +
1245 +#define MTK_PPE_BIND_RATE 0x228
1246 +#define MTK_PPE_BIND_RATE_BIND GENMASK(15, 0)
1247 +#define MTK_PPE_BIND_RATE_PREBIND GENMASK(31, 16)
1248 +
1249 +#define MTK_PPE_BIND_LIMIT0 0x22c
1250 +#define MTK_PPE_BIND_LIMIT0_QUARTER GENMASK(13, 0)
1251 +#define MTK_PPE_BIND_LIMIT0_HALF GENMASK(29, 16)
1252 +
1253 +#define MTK_PPE_BIND_LIMIT1 0x230
1254 +#define MTK_PPE_BIND_LIMIT1_FULL GENMASK(13, 0)
1255 +#define MTK_PPE_BIND_LIMIT1_NON_L4 GENMASK(23, 16)
1256 +
1257 +#define MTK_PPE_KEEPALIVE 0x234
1258 +#define MTK_PPE_KEEPALIVE_TIME GENMASK(15, 0)
1259 +#define MTK_PPE_KEEPALIVE_TIME_TCP GENMASK(23, 16)
1260 +#define MTK_PPE_KEEPALIVE_TIME_UDP GENMASK(31, 24)
1261 +
1262 +#define MTK_PPE_UNBIND_AGE 0x238
1263 +#define MTK_PPE_UNBIND_AGE_MIN_PACKETS GENMASK(31, 16)
1264 +#define MTK_PPE_UNBIND_AGE_DELTA GENMASK(7, 0)
1265 +
1266 +#define MTK_PPE_BIND_AGE0 0x23c
1267 +#define MTK_PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16)
1268 +#define MTK_PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0)
1269 +
1270 +#define MTK_PPE_BIND_AGE1 0x240
1271 +#define MTK_PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16)
1272 +#define MTK_PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0)
1273 +
1274 +#define MTK_PPE_HASH_SEED 0x244
1275 +
1276 +#define MTK_PPE_DEFAULT_CPU_PORT 0x248
1277 +#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4))
1278 +
1279 +#define MTK_PPE_MTU_DROP 0x308
1280 +
1281 +#define MTK_PPE_VLAN_MTU0 0x30c
1282 +#define MTK_PPE_VLAN_MTU0_NONE GENMASK(13, 0)
1283 +#define MTK_PPE_VLAN_MTU0_1TAG GENMASK(29, 16)
1284 +
1285 +#define MTK_PPE_VLAN_MTU1 0x310
1286 +#define MTK_PPE_VLAN_MTU1_2TAG GENMASK(13, 0)
1287 +#define MTK_PPE_VLAN_MTU1_3TAG GENMASK(29, 16)
1288 +
1289 +#define MTK_PPE_VPM_TPID 0x318
1290 +
1291 +#define MTK_PPE_CACHE_CTL 0x320
1292 +#define MTK_PPE_CACHE_CTL_EN BIT(0)
1293 +#define MTK_PPE_CACHE_CTL_LOCK_CLR BIT(4)
1294 +#define MTK_PPE_CACHE_CTL_REQ BIT(8)
1295 +#define MTK_PPE_CACHE_CTL_CLEAR BIT(9)
1296 +#define MTK_PPE_CACHE_CTL_CMD GENMASK(13, 12)
1297 +
1298 +#define MTK_PPE_MIB_CFG 0x334
1299 +#define MTK_PPE_MIB_CFG_EN BIT(0)
1300 +#define MTK_PPE_MIB_CFG_RD_CLR BIT(1)
1301 +
1302 +#define MTK_PPE_MIB_TB_BASE 0x338
1303 +
1304 +#define MTK_PPE_MIB_CACHE_CTL 0x350
1305 +#define MTK_PPE_MIB_CACHE_CTL_EN BIT(0)
1306 +#define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2)
1307 +
1308 +#endif
Staging tree of Stijn Tintel