projects / openwrt / staging / dangole.git / blob
? search:


9bdce0493ef07c7d285b65e1e121ef67c844fa0b
[openwrt/staging/dangole.git] /
1 From 05aba5763dcf35eddc58aaf99c9f16d19730e0a8 Mon Sep 17 00:00:00 2001
2 From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
3 Date: Thu, 27 Oct 2016 11:55:39 +0200
4 Subject: [PATCH] mtd: spi-nor: rename SPINOR_OP_* macros of the 4-byte address
5 op codes
6
7 This patch renames the SPINOR_OP_* macros of the 4-byte address
8 instruction set so the new names all share a common pattern: the 4-byte
9 address name is built from the 3-byte address name appending the "_4B"
10 suffix.
11
12 The patch also introduces new op codes to support other SPI protocols such
13 as SPI 1-4-4 and SPI 1-2-2.
14
15 This is a transitional patch and will help a later patch of spi-nor.c
16 to automate the translation from the 3-byte address op codes into their
17 4-byte address version.
18
19 Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
20 Acked-by: Mark Brown <broonie@kernel.org>
21 Acked-by: Marek Vasut <marek.vasut@gmail.com>
22 ---
23 drivers/mtd/devices/serial_flash_cmds.h | 7 -------
24 drivers/mtd/devices/st_spi_fsm.c | 28 ++++++++++++++--------------
25 drivers/mtd/spi-nor/spi-nor.c | 8 ++++----
26 drivers/spi/spi-bcm-qspi.c | 6 +++---
27 include/linux/mtd/spi-nor.h | 22 ++++++++++++++++------
28 5 files changed, 37 insertions(+), 34 deletions(-)
29
30 --- a/drivers/mtd/devices/serial_flash_cmds.h
31 +++ b/drivers/mtd/devices/serial_flash_cmds.h
32 @@ -18,19 +18,12 @@
33 #define SPINOR_OP_RDVCR 0x85
34
35 /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
36 -#define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */
37 -#define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */
38 -
39 #define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */
40 #define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
41 #define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
42 #define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
43 #define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
44
45 -/* READ commands with 32-bit addressing */
46 -#define SPINOR_OP_READ4_1_2_2 0xbc
47 -#define SPINOR_OP_READ4_1_4_4 0xec
48 -
49 /* Configuration flags */
50 #define FLASH_FLAG_SINGLE 0x000000ff
51 #define FLASH_FLAG_READ_WRITE 0x00000001
52 --- a/drivers/mtd/devices/st_spi_fsm.c
53 +++ b/drivers/mtd/devices/st_spi_fsm.c
54 @@ -507,13 +507,13 @@ static struct seq_rw_config n25q_read3_c
55 * - 'FAST' variants configured for 8 dummy cycles (see note above.)
56 */
57 static struct seq_rw_config n25q_read4_configs[] = {
58 - {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8},
59 - {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
60 - {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8},
61 - {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
62 - {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
63 - {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
64 - {0x00, 0, 0, 0, 0, 0x00, 0, 0},
65 + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 0, 8},
66 + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
67 + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 0, 8},
68 + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
69 + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
70 + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
71 + {0x00, 0, 0, 0, 0, 0x00, 0, 0},
72 };
73
74 /*
75 @@ -553,13 +553,13 @@ static int stfsm_mx25_en_32bit_addr_seq(
76 * entering a state that is incompatible with the SPIBoot Controller.
77 */
78 static struct seq_rw_config stfsm_s25fl_read4_configs[] = {
79 - {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4},
80 - {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
81 - {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0},
82 - {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
83 - {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
84 - {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
85 - {0x00, 0, 0, 0, 0, 0x00, 0, 0},
86 + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 2, 4},
87 + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
88 + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 4, 0},
89 + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
90 + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
91 + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
92 + {0x00, 0, 0, 0, 0, 0x00, 0, 0},
93 };
94
95 static struct seq_rw_config stfsm_s25fl_write4_configs[] = {
96 --- a/drivers/mtd/spi-nor/spi-nor.c
97 +++ b/drivers/mtd/spi-nor/spi-nor.c
98 @@ -1625,16 +1625,16 @@ int spi_nor_scan(struct spi_nor *nor, co
99 /* Dedicated 4-byte command set */
100 switch (nor->flash_read) {
101 case SPI_NOR_QUAD:
102 - nor->read_opcode = SPINOR_OP_READ4_1_1_4;
103 + nor->read_opcode = SPINOR_OP_READ_1_1_4_4B;
104 break;
105 case SPI_NOR_DUAL:
106 - nor->read_opcode = SPINOR_OP_READ4_1_1_2;
107 + nor->read_opcode = SPINOR_OP_READ_1_1_2_4B;
108 break;
109 case SPI_NOR_FAST:
110 - nor->read_opcode = SPINOR_OP_READ4_FAST;
111 + nor->read_opcode = SPINOR_OP_READ_FAST_4B;
112 break;
113 case SPI_NOR_NORMAL:
114 - nor->read_opcode = SPINOR_OP_READ4;
115 + nor->read_opcode = SPINOR_OP_READ_4B;
116 break;
117 }
118 nor->program_opcode = SPINOR_OP_PP_4B;
119 --- a/drivers/spi/spi-bcm-qspi.c
120 +++ b/drivers/spi/spi-bcm-qspi.c
121 @@ -371,7 +371,7 @@ static int bcm_qspi_bspi_set_flex_mode(s
122 /* default mode, does not need flex_cmd */
123 flex_mode = 0;
124 else
125 - command = SPINOR_OP_READ4_FAST;
126 + command = SPINOR_OP_READ_FAST_4B;
127 break;
128 case SPI_NBITS_DUAL:
129 bpc = 0x00000001;
130 @@ -384,7 +384,7 @@ static int bcm_qspi_bspi_set_flex_mode(s
131 } else {
132 command = SPINOR_OP_READ_1_1_2;
133 if (spans_4byte)
134 - command = SPINOR_OP_READ4_1_1_2;
135 + command = SPINOR_OP_READ_1_1_2_4B;
136 }
137 break;
138 case SPI_NBITS_QUAD:
139 @@ -399,7 +399,7 @@ static int bcm_qspi_bspi_set_flex_mode(s
140 } else {
141 command = SPINOR_OP_READ_1_1_4;
142 if (spans_4byte)
143 - command = SPINOR_OP_READ4_1_1_4;
144 + command = SPINOR_OP_READ_1_1_4_4B;
145 }
146 break;
147 default:
148 --- a/include/linux/mtd/spi-nor.h
149 +++ b/include/linux/mtd/spi-nor.h
150 @@ -43,9 +43,13 @@
151 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
152 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
153 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
154 -#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
155 -#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
156 +#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
157 +#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
158 +#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
159 +#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
160 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
161 +#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
162 +#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
163 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
164 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
165 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
166 @@ -56,11 +60,17 @@
167 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
168
169 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
170 -#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
171 -#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
172 -#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
173 -#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
174 +#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
175 +#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
176 +#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
177 +#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
178 +#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
179 +#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
180 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
181 +#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
182 +#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
183 +#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
184 +#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
185 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
186
187 /* Used for SST flashes only. */
Staging tree of Daniel Golle