git.openwrt.org Git - openwrt/staging/robimarko.git/blob

   1 From 0ba6ff7f5632f01143911e307be538ecc62e5094 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Thu, 19 Aug 2021 15:59:30 +0200
   4 Subject: [PATCH] drm/vc4: hdmi: Make sure the device is powered with
   5  CEC
   6
   7 Similarly to what we encountered with the detect hook with DRM, nothing
   8 actually prevents any of the CEC callback from being run while the HDMI
   9 output is disabled.
  10
  11 However, this is an issue since any register access to the controller
  12 when it's powered down will result in a silent hang.
  13
  14 Let's make sure we run the runtime_pm hooks when the CEC adapter is
  15 opened and closed by the userspace to avoid that issue.
  16
  17 Fixes: 15b4511a4af6 ("drm/vc4: add HDMI CEC support")
  18 Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  19 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  20 Link: https://patchwork.freedesktop.org/patch/msgid/20210819135931.895976-6-maxime@cerno.tech
  21 ---
  22  drivers/gpu/drm/vc4/vc4_hdmi.c | 10 +++++++++-
  23  1 file changed, 9 insertions(+), 1 deletion(-)
  24
  25 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  26 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  27 @@ -1744,8 +1744,14 @@ static int vc4_hdmi_cec_enable(struct ce
  28         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
  29         /* clock period in microseconds */
  30         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
  31 -       u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
  32 +       u32 val;
  33 +       int ret;
  34
  35 +       ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
  36 +       if (ret)
  37 +               return ret;
  38 +
  39 +       val = HDMI_READ(HDMI_CEC_CNTRL_5);
  40         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
  41                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
  42                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
  43 @@ -1788,6 +1794,8 @@ static int vc4_hdmi_cec_disable(struct c
  44         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
  45                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
  46
  47 +       pm_runtime_put(&vc4_hdmi->pdev->dev);
  48 +
  49         return 0;
  50  }
  51