git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 92c6f000cb3a4280166d812d88cda3011717b548 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Wed, 7 Dec 2016 08:56:55 +0100
   4 Subject: [PATCH 6/6] ARM: BCM53573: Specify USB ports of on-SoC controllers
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Broadcom OHCI and EHCI controllers always have 2 ports each on the root
  10 hub. Describe them in DT to allow specifying extra info or referencing
  11 port nodes.
  12
  13 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  14 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  15 ---
  16  arch/arm/boot/dts/bcm53573.dtsi | 22 ++++++++++++++++++++++
  17  1 file changed, 22 insertions(+)
  18
  19 --- a/arch/arm/boot/dts/bcm53573.dtsi
  20 +++ b/arch/arm/boot/dts/bcm53573.dtsi
  21 @@ -124,6 +124,17 @@
  22                                 reg = <0x4000 0x1000>;
  23                                 interrupt-parent = <&gic>;
  24                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  25 +
  26 +                               #address-cells = <1>;
  27 +                               #size-cells = <0>;
  28 +
  29 +                               ehci_port1: port@1 {
  30 +                                       reg = <1>;
  31 +                               };
  32 +
  33 +                               ehci_port2: port@2 {
  34 +                                       reg = <2>;
  35 +                               };
  36                         };
  37
  38                         ohci: ohci@d000 {
  39 @@ -133,6 +144,17 @@
  40                                 reg = <0xd000 0x1000>;
  41                                 interrupt-parent = <&gic>;
  42                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  43 +
  44 +                               #address-cells = <1>;
  45 +                               #size-cells = <0>;
  46 +
  47 +                               ohci_port1: port@1 {
  48 +                                       reg = <1>;
  49 +                               };
  50 +
  51 +                               ohci_port2: port@2 {
  52 +                                       reg = <2>;
  53 +                               };
  54                         };
  55                 };
  56