git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001
   2 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   3 Date: Mon, 6 Mar 2023 15:05:21 +0100
   4 Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set
   5  critical clock
   6
   7 Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
   8 flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
   9
  10 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  11 Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
  12 Tested-by: Daniel Golle <daniel@makrotopia.org>
  13 Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
  14 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  15 ---
  16  drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +---
  17  1 file changed, 1 insertion(+), 3 deletions(-)
  18
  19 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
  20 +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
  21 @@ -42,7 +42,7 @@
  22                  "clkxtal")
  23
  24  static const struct mtk_pll_data plls[] = {
  25 -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
  26 +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
  27             0x0200, 4, 0, 0x0204, 0),
  28         PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
  29             0x0210, 4, 0, 0x0214, 0),
  30 @@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru
  31
  32         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  33
  34 -       clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
  35 -
  36         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  37         if (r) {
  38                 pr_err("%s(): could not register clock provider: %d\n",