git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001
   2 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   3 Date: Fri, 20 Jan 2023 10:20:36 +0100
   4 Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for
   5  mtk-mux
   6
   7 Like done for other clocks, propagate struct device for mtk mux clocks
   8 registered through clk-mux helpers to enable runtime pm support.
   9
  10 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  11 Tested-by: Miles Chen <miles.chen@mediatek.com>
  12 Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com
  13 Tested-by: Mingming Su <mingming.su@mediatek.com>
  14 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  15
  16 [daniel@makrotopia.org: removed parts not relevant for OpenWrt]
  17 ---
  18  drivers/clk/mediatek/clk-mt7986-infracfg.c |  3 ++-
  19  drivers/clk/mediatek/clk-mt7986-topckgen.c |  3 ++-
  20  drivers/clk/mediatek/clk-mux.c             | 14 ++++++++------
  21  drivers/clk/mediatek/clk-mux.h             |  3 ++-
  22  4 files changed, 14 insertions(+), 9 deletions(-)
  23
  24 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
  25 +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
  26 @@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str
  27                 return -ENOMEM;
  28
  29         mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
  30 -       mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
  31 +       mtk_clk_register_muxes(&pdev->dev, infra_muxes,
  32 +                              ARRAY_SIZE(infra_muxes), node,
  33                                &mt7986_clk_lock, clk_data);
  34         mtk_clk_register_gates(&pdev->dev, node, infra_clks,
  35                                ARRAY_SIZE(infra_clks), clk_data);
  36 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
  37 +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
  38 @@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str
  39         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  40                                     clk_data);
  41         mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
  42 -       mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
  43 +       mtk_clk_register_muxes(&pdev->dev, top_muxes,
  44 +                              ARRAY_SIZE(top_muxes), node,
  45                                &mt7986_clk_lock, clk_data);
  46
  47         clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
  48 --- a/drivers/clk/mediatek/clk-mux.c
  49 +++ b/drivers/clk/mediatek/clk-mux.c
  50 @@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se
  51  };
  52  EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
  53
  54 -static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux,
  55 -                                struct regmap *regmap,
  56 -                                spinlock_t *lock)
  57 +static struct clk_hw *mtk_clk_register_mux(struct device *dev,
  58 +                                          const struct mtk_mux *mux,
  59 +                                          struct regmap *regmap,
  60 +                                          spinlock_t *lock)
  61  {
  62         struct mtk_clk_mux *clk_mux;
  63         struct clk_init_data init = {};
  64 @@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m
  65         clk_mux->lock = lock;
  66         clk_mux->hw.init = &init;
  67
  68 -       ret = clk_hw_register(NULL, &clk_mux->hw);
  69 +       ret = clk_hw_register(dev, &clk_mux->hw);
  70         if (ret) {
  71                 kfree(clk_mux);
  72                 return ERR_PTR(ret);
  73 @@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc
  74         kfree(mux);
  75  }
  76
  77 -int mtk_clk_register_muxes(const struct mtk_mux *muxes,
  78 +int mtk_clk_register_muxes(struct device *dev,
  79 +                          const struct mtk_mux *muxes,
  80                            int num, struct device_node *node,
  81                            spinlock_t *lock,
  82                            struct clk_hw_onecell_data *clk_data)
  83 @@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct
  84                         continue;
  85                 }
  86
  87 -               hw = mtk_clk_register_mux(mux, regmap, lock);
  88 +               hw = mtk_clk_register_mux(dev, mux, regmap, lock);
  89
  90                 if (IS_ERR(hw)) {
  91                         pr_err("Failed to register clk %s: %pe\n", mux->name,
  92 --- a/drivers/clk/mediatek/clk-mux.h
  93 +++ b/drivers/clk/mediatek/clk-mux.h
  94 @@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate
  95                         0, _upd_ofs, _upd, CLK_SET_RATE_PARENT,         \
  96                         mtk_mux_clr_set_upd_ops)
  97
  98 -int mtk_clk_register_muxes(const struct mtk_mux *muxes,
  99 +int mtk_clk_register_muxes(struct device *dev,
 100 +                          const struct mtk_mux *muxes,
 101                            int num, struct device_node *node,
 102                            spinlock_t *lock,
 103                            struct clk_hw_onecell_data *clk_data);