a61dc66bf6204f4191e4801f2deed89b709bd8f7
[openwrt/staging/dangole.git] /
1 From 7f98947db09ad419ca73082230ade1f29f18bd82 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Mon, 6 Mar 2017 12:17:16 -0800
4 Subject: [PATCH 128/454] panel-raspberrypi-touchscreen: Round up clk rate to
5 fix DSI panel.
6
7 Commit 488f9bc8e3def93e0baef53cee2026c2cb0d8956 slightly increased the
8 reported rate of PLLD, so the clk driver decided that PLLD/3/8 was now
9 higher than our requested pixel clock rate and rejected it in favor of
10 PLLD/4/8, which then ran the pixel clock way out of spec.
11
12 By bumping the requested clock rate just slightly, we get back to
13 PLLD/3/8 like we wanted and the panel displays content again.
14
15 Signed-off-by: Eric Anholt <eric@anholt.net>
16 ---
17 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c | 7 ++++++-
18 1 file changed, 6 insertions(+), 1 deletion(-)
19
20 --- a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
21 +++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
22 @@ -220,7 +220,12 @@ static const struct drm_display_mode rpi
23 #define HBP 46
24 #define HFP ((PIXEL_CLOCK / (VTOTAL * VREFRESH)) - (HACT + HSW + HBP))
25
26 - .clock = PIXEL_CLOCK / 1000,
27 + /* Round up the pixel clock a bit (10khz), so that the
28 + * "don't run things faster than the requested clock
29 + * rate" rule of the clk driver doesn't reject the
30 + * divide-by-3 mode due to rounding error.
31 + */
32 + .clock = PIXEL_CLOCK / 1000 + 10,
33 .hdisplay = HACT,
34 .hsync_start = HACT + HFP,
35 .hsync_end = HACT + HFP + HSW,