projects / openwrt / staging / linusw.git / blob
? search:


aa82f3c7e153c93e03064308c467d124e2493100
[openwrt/staging/linusw.git] /
1 From 2a2c0889e2695a39ea0479b5ebe30bd8ff8e3f21 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Mon, 14 Feb 2022 17:21:05 +0100
4 Subject: [PATCH] drm/vc4: hvs: Use pointer to HVS in HVS_READ and
5 HVS_WRITE macros
6
7 Those macros are really about the HVS itself, and thus its associated
8 structure vc4_hvs, rather than the entire (virtual) vc4 device.
9
10 Let's change those macros to use the hvs pointer directly, and change
11 the calling sites accordingly.
12
13 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
14 ---
15 drivers/gpu/drm/vc4/vc4_crtc.c | 14 +++--
16 drivers/gpu/drm/vc4/vc4_drv.h | 16 ++---
17 drivers/gpu/drm/vc4/vc4_hvs.c | 109 +++++++++++++++++----------------
18 drivers/gpu/drm/vc4/vc4_kms.c | 5 +-
19 4 files changed, 77 insertions(+), 67 deletions(-)
20
21 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
22 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
23 @@ -70,6 +70,7 @@ static const struct debugfs_reg32 crtc_r
24 static unsigned int
25 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
26 {
27 + struct vc4_hvs *hvs = vc4->hvs;
28 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
29 /* Top/base are supposed to be 4-pixel aligned, but the
30 * Raspberry Pi firmware fills the low bits (which are
31 @@ -89,6 +90,7 @@ static bool vc4_crtc_get_scanout_positio
32 {
33 struct drm_device *dev = crtc->dev;
34 struct vc4_dev *vc4 = to_vc4_dev(dev);
35 + struct vc4_hvs *hvs = vc4->hvs;
36 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
37 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
38 unsigned int cob_size;
39 @@ -123,7 +125,7 @@ static bool vc4_crtc_get_scanout_positio
40 *vpos /= 2;
41
42 /* Use hpos to correct for field offset in interlaced mode. */
43 - if (vc4_hvs_get_fifo_frame_count(dev, vc4_crtc_state->assigned_channel) % 2)
44 + if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2)
45 *hpos += mode->crtc_htotal / 2;
46 }
47
48 @@ -433,6 +435,7 @@ static void vc4_crtc_config_pv(struct dr
49 static void require_hvs_enabled(struct drm_device *dev)
50 {
51 struct vc4_dev *vc4 = to_vc4_dev(dev);
52 + struct vc4_hvs *hvs = vc4->hvs;
53
54 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
55 SCALER_DISPCTRL_ENABLE);
56 @@ -446,6 +449,7 @@ static int vc4_crtc_disable(struct drm_c
57 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
58 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
59 struct drm_device *dev = crtc->dev;
60 + struct vc4_dev *vc4 = to_vc4_dev(dev);
61 int ret;
62
63 CRTC_WRITE(PV_V_CONTROL,
64 @@ -475,7 +479,7 @@ static int vc4_crtc_disable(struct drm_c
65 vc4_encoder->post_crtc_disable(encoder, state);
66
67 vc4_crtc_pixelvalve_reset(crtc);
68 - vc4_hvs_stop_channel(dev, channel);
69 + vc4_hvs_stop_channel(vc4->hvs, channel);
70
71 if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
72 vc4_encoder->post_crtc_powerdown(encoder, state);
73 @@ -501,6 +505,7 @@ static struct drm_encoder *vc4_crtc_get_
74 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
75 {
76 struct drm_device *drm = crtc->dev;
77 + struct vc4_dev *vc4 = to_vc4_dev(drm);
78 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
79 enum vc4_encoder_type encoder_type;
80 const struct vc4_pv_data *pv_data;
81 @@ -522,7 +527,7 @@ int vc4_crtc_disable_at_boot(struct drm_
82 if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
83 return 0;
84
85 - channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output);
86 + channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
87 if (channel < 0)
88 return 0;
89
90 @@ -738,6 +743,7 @@ static void vc4_crtc_handle_page_flip(st
91 struct drm_crtc *crtc = &vc4_crtc->base;
92 struct drm_device *dev = crtc->dev;
93 struct vc4_dev *vc4 = to_vc4_dev(dev);
94 + struct vc4_hvs *hvs = vc4->hvs;
95 u32 chan = vc4_crtc->current_hvs_channel;
96 unsigned long flags;
97
98 @@ -756,7 +762,7 @@ static void vc4_crtc_handle_page_flip(st
99 * the CRTC and encoder already reconfigured, leading to
100 * underruns. This can be seen when reconfiguring the CRTC.
101 */
102 - vc4_hvs_unmask_underrun(dev, chan);
103 + vc4_hvs_unmask_underrun(hvs, chan);
104 }
105 spin_unlock(&vc4_crtc->irq_lock);
106 spin_unlock_irqrestore(&dev->event_lock, flags);
107 --- a/drivers/gpu/drm/vc4/vc4_drv.h
108 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
109 @@ -603,8 +603,8 @@ to_vc4_crtc_state(struct drm_crtc_state
110
111 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
112 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
113 -#define HVS_READ(offset) readl(vc4->hvs->regs + offset)
114 -#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
115 +#define HVS_READ(offset) readl(hvs->regs + offset)
116 +#define HVS_WRITE(offset, val) writel(val, hvs->regs + offset)
117
118 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
119
120 @@ -965,17 +965,17 @@ void vc4_irq_reset(struct drm_device *de
121
122 /* vc4_hvs.c */
123 extern struct platform_driver vc4_hvs_driver;
124 -void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
125 -int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
126 -u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo);
127 +void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int output);
128 +int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output);
129 +u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo);
130 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
131 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state);
132 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
133 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);
134 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);
135 -void vc4_hvs_dump_state(struct drm_device *dev);
136 -void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
137 -void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
138 +void vc4_hvs_dump_state(struct vc4_hvs *hvs);
139 +void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel);
140 +void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel);
141
142 /* vc4_kms.c */
143 int vc4_kms_load(struct drm_device *dev);
144 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
145 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
146 @@ -64,22 +64,21 @@ static const struct debugfs_reg32 hvs_re
147 VC4_REG32(SCALER_OLEDCOEF2),
148 };
149
150 -void vc4_hvs_dump_state(struct drm_device *dev)
151 +void vc4_hvs_dump_state(struct vc4_hvs *hvs)
152 {
153 - struct vc4_dev *vc4 = to_vc4_dev(dev);
154 - struct drm_printer p = drm_info_printer(&vc4->hvs->pdev->dev);
155 + struct drm_printer p = drm_info_printer(&hvs->pdev->dev);
156 int i;
157
158 - drm_print_regset32(&p, &vc4->hvs->regset);
159 + drm_print_regset32(&p, &hvs->regset);
160
161 DRM_INFO("HVS ctx:\n");
162 for (i = 0; i < 64; i += 4) {
163 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
164 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
165 - readl((u32 __iomem *)vc4->hvs->dlist + i + 0),
166 - readl((u32 __iomem *)vc4->hvs->dlist + i + 1),
167 - readl((u32 __iomem *)vc4->hvs->dlist + i + 2),
168 - readl((u32 __iomem *)vc4->hvs->dlist + i + 3));
169 + readl((u32 __iomem *)hvs->dlist + i + 0),
170 + readl((u32 __iomem *)hvs->dlist + i + 1),
171 + readl((u32 __iomem *)hvs->dlist + i + 2),
172 + readl((u32 __iomem *)hvs->dlist + i + 3));
173 }
174 }
175
176 @@ -100,6 +99,7 @@ static int vc4_hvs_debugfs_dlist(struct
177 struct drm_info_node *node = m->private;
178 struct drm_device *dev = node->minor->dev;
179 struct vc4_dev *vc4 = to_vc4_dev(dev);
180 + struct vc4_hvs *hvs = vc4->hvs;
181 struct drm_printer p = drm_seq_file_printer(m);
182 unsigned int next_entry_start = 0;
183 unsigned int i, j;
184 @@ -139,6 +139,7 @@ static int vc5_hvs_debugfs_gamma(struct
185 struct drm_info_node *node = m->private;
186 struct drm_device *dev = node->minor->dev;
187 struct vc4_dev *vc4 = to_vc4_dev(dev);
188 + struct vc4_hvs *hvs = vc4->hvs;
189 struct drm_printer p = drm_seq_file_printer(m);
190 unsigned int i, chan;
191 u32 dispstat, dispbkgndx;
192 @@ -274,11 +275,10 @@ static int vc4_hvs_upload_linear_kernel(
193 return 0;
194 }
195
196 -static void vc4_hvs_lut_load(struct drm_crtc *crtc)
197 +static void vc4_hvs_lut_load(struct vc4_hvs *hvs,
198 + struct vc4_crtc *vc4_crtc)
199 {
200 - struct drm_device *dev = crtc->dev;
201 - struct vc4_dev *vc4 = to_vc4_dev(dev);
202 - struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
203 + struct drm_crtc *crtc = &vc4_crtc->base;
204 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
205 u32 i;
206
207 @@ -298,11 +298,12 @@ static void vc4_hvs_lut_load(struct drm_
208 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
209 }
210
211 -static void vc4_hvs_update_gamma_lut(struct drm_crtc *crtc)
212 +static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs,
213 + struct vc4_crtc *vc4_crtc)
214 {
215 - struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
216 - struct drm_color_lut *lut = crtc->state->gamma_lut->data;
217 - u32 length = drm_color_lut_size(crtc->state->gamma_lut);
218 + struct drm_crtc_state *crtc_state = vc4_crtc->base.state;
219 + struct drm_color_lut *lut = crtc_state->gamma_lut->data;
220 + u32 length = drm_color_lut_size(crtc_state->gamma_lut);
221 u32 i;
222
223 for (i = 0; i < length; i++) {
224 @@ -311,12 +312,11 @@ static void vc4_hvs_update_gamma_lut(str
225 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
226 }
227
228 - vc4_hvs_lut_load(crtc);
229 + vc4_hvs_lut_load(hvs, vc4_crtc);
230 }
231
232 -u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo)
233 +u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
234 {
235 - struct vc4_dev *vc4 = to_vc4_dev(dev);
236 u8 field = 0;
237
238 switch (fifo) {
239 @@ -337,7 +337,7 @@ u8 vc4_hvs_get_fifo_frame_count(struct d
240 return field;
241 }
242
243 -static void vc5_hvs_write_gamma_entry(struct vc4_dev *vc4,
244 +static void vc5_hvs_write_gamma_entry(struct vc4_hvs *hvs,
245 u32 offset,
246 struct vc5_gamma_entry *gamma)
247 {
248 @@ -345,33 +345,33 @@ static void vc5_hvs_write_gamma_entry(st
249 HVS_WRITE(offset + 4, gamma->grad_term);
250 }
251
252 -static void vc5_hvs_lut_load(struct drm_crtc *crtc)
253 +static void vc5_hvs_lut_load(struct vc4_hvs *hvs,
254 + struct vc4_crtc *vc4_crtc)
255 {
256 - struct drm_device *dev = crtc->dev;
257 - struct vc4_dev *vc4 = to_vc4_dev(dev);
258 - struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
259 - struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
260 + struct drm_crtc_state *crtc_state = vc4_crtc->base.state;
261 + struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
262 u32 i;
263 u32 offset = SCALER5_DSPGAMMA_START +
264 vc4_state->assigned_channel * SCALER5_DSPGAMMA_CHAN_OFFSET;
265
266 for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
267 - vc5_hvs_write_gamma_entry(vc4, offset, &vc4_crtc->pwl_r[i]);
268 + vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_r[i]);
269 for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
270 - vc5_hvs_write_gamma_entry(vc4, offset, &vc4_crtc->pwl_g[i]);
271 + vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_g[i]);
272 for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
273 - vc5_hvs_write_gamma_entry(vc4, offset, &vc4_crtc->pwl_b[i]);
274 + vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_b[i]);
275
276 if (vc4_state->assigned_channel == 2) {
277 /* Alpha only valid on channel 2 */
278 for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
279 - vc5_hvs_write_gamma_entry(vc4, offset, &vc4_crtc->pwl_a[i]);
280 + vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_a[i]);
281 }
282 }
283
284 -static void vc5_hvs_update_gamma_lut(struct drm_crtc *crtc)
285 +static void vc5_hvs_update_gamma_lut(struct vc4_hvs *hvs,
286 + struct vc4_crtc *vc4_crtc)
287 {
288 - struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
289 + struct drm_crtc *crtc = &vc4_crtc->base;
290 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
291 unsigned int step, i;
292 u32 start, end;
293 @@ -408,16 +408,15 @@ static void vc5_hvs_update_gamma_lut(str
294 VC5_HVS_UPDATE_GAMMA_ENTRY_FROM_LUT(pwl_b, blue);
295 }
296
297 - vc5_hvs_lut_load(crtc);
298 + vc5_hvs_lut_load(hvs, vc4_crtc);
299 }
300
301 -int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output)
302 +int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
303 {
304 - struct vc4_dev *vc4 = to_vc4_dev(dev);
305 u32 reg;
306 int ret;
307
308 - if (!vc4->hvs->hvs5)
309 + if (!hvs->hvs5)
310 return output;
311
312 switch (output) {
313 @@ -464,9 +463,10 @@ int vc4_hvs_get_fifo_from_output(struct
314 }
315 }
316
317 -static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
318 +static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
319 struct drm_display_mode *mode, bool oneshot)
320 {
321 + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
322 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
323 unsigned int chan = vc4_crtc_state->assigned_channel;
324 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
325 @@ -484,7 +484,7 @@ static int vc4_hvs_init_channel(struct v
326 */
327 dispctrl = SCALER_DISPCTRLX_ENABLE;
328
329 - if (!vc4->hvs->hvs5)
330 + if (!hvs->hvs5)
331 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
332 SCALER_DISPCTRLX_WIDTH) |
333 VC4_SET_FIELD(mode->vdisplay,
334 @@ -514,18 +514,16 @@ static int vc4_hvs_init_channel(struct v
335 /* Reload the LUT, since the SRAMs would have been disabled if
336 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
337 */
338 - if (!vc4->hvs->hvs5)
339 - vc4_hvs_lut_load(crtc);
340 + if (!hvs->hvs5)
341 + vc4_hvs_lut_load(hvs, vc4_crtc);
342 else
343 - vc5_hvs_lut_load(crtc);
344 + vc5_hvs_lut_load(hvs, vc4_crtc);
345
346 return 0;
347 }
348
349 -void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int chan)
350 +void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
351 {
352 - struct vc4_dev *vc4 = to_vc4_dev(dev);
353 -
354 if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE)
355 return;
356
357 @@ -623,6 +621,7 @@ static void vc4_hvs_install_dlist(struct
358 {
359 struct drm_device *dev = crtc->dev;
360 struct vc4_dev *vc4 = to_vc4_dev(dev);
361 + struct vc4_hvs *hvs = vc4->hvs;
362 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
363
364 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
365 @@ -679,18 +678,19 @@ void vc4_hvs_atomic_enable(struct drm_cr
366
367 vc4_hvs_install_dlist(crtc);
368 vc4_hvs_update_dlist(crtc);
369 - vc4_hvs_init_channel(vc4, crtc, mode, oneshot);
370 + vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot);
371 }
372
373 void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
374 struct drm_atomic_state *state)
375 {
376 struct drm_device *dev = crtc->dev;
377 + struct vc4_dev *vc4 = to_vc4_dev(dev);
378 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
379 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state);
380 unsigned int chan = vc4_state->assigned_channel;
381
382 - vc4_hvs_stop_channel(dev, chan);
383 + vc4_hvs_stop_channel(vc4->hvs, chan);
384 }
385
386 void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
387 @@ -700,6 +700,8 @@ void vc4_hvs_atomic_flush(struct drm_crt
388 crtc);
389 struct drm_device *dev = crtc->dev;
390 struct vc4_dev *vc4 = to_vc4_dev(dev);
391 + struct vc4_hvs *hvs = vc4->hvs;
392 + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
393 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
394 unsigned int channel = vc4_state->assigned_channel;
395 struct drm_plane *plane;
396 @@ -714,7 +716,7 @@ void vc4_hvs_atomic_flush(struct drm_crt
397
398 if (debug_dump_regs) {
399 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
400 - vc4_hvs_dump_state(dev);
401 + vc4_hvs_dump_state(hvs);
402 }
403
404 /* Copy all the active planes' dlist contents to the hardware dlist. */
405 @@ -766,10 +768,10 @@ void vc4_hvs_atomic_flush(struct drm_crt
406
407 if (crtc->state->gamma_lut) {
408 if (!vc4->hvs->hvs5) {
409 - vc4_hvs_update_gamma_lut(crtc);
410 + vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
411 dispbkgndx |= SCALER_DISPBKGND_GAMMA;
412 } else {
413 - vc5_hvs_update_gamma_lut(crtc);
414 + vc5_hvs_update_gamma_lut(hvs, vc4_crtc);
415 }
416 } else {
417 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
418 @@ -790,13 +792,12 @@ void vc4_hvs_atomic_flush(struct drm_crt
419
420 if (debug_dump_regs) {
421 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
422 - vc4_hvs_dump_state(dev);
423 + vc4_hvs_dump_state(hvs);
424 }
425 }
426
427 -void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
428 +void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel)
429 {
430 - struct vc4_dev *vc4 = to_vc4_dev(dev);
431 u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
432
433 dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
434 @@ -804,9 +805,8 @@ void vc4_hvs_mask_underrun(struct drm_de
435 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
436 }
437
438 -void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)
439 +void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel)
440 {
441 - struct vc4_dev *vc4 = to_vc4_dev(dev);
442 u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
443
444 dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
445 @@ -828,6 +828,7 @@ static irqreturn_t vc4_hvs_irq_handler(i
446 {
447 struct drm_device *dev = data;
448 struct vc4_dev *vc4 = to_vc4_dev(dev);
449 + struct vc4_hvs *hvs = vc4->hvs;
450 irqreturn_t irqret = IRQ_NONE;
451 int channel;
452 u32 control;
453 @@ -840,7 +841,7 @@ static irqreturn_t vc4_hvs_irq_handler(i
454 /* Interrupt masking is not always honored, so check it here. */
455 if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
456 control & SCALER_DISPCTRL_DSPEISLUR(channel)) {
457 - vc4_hvs_mask_underrun(dev, channel);
458 + vc4_hvs_mask_underrun(hvs, channel);
459 vc4_hvs_report_underrun(dev);
460
461 irqret = IRQ_HANDLED;
462 --- a/drivers/gpu/drm/vc4/vc4_kms.c
463 +++ b/drivers/gpu/drm/vc4/vc4_kms.c
464 @@ -158,6 +158,7 @@ static u16 vc4_ctm_s31_32_to_s0_9(u64 in
465 static void
466 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
467 {
468 + struct vc4_hvs *hvs = vc4->hvs;
469 struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
470 struct drm_color_ctm *ctm = ctm_state->ctm;
471
472 @@ -234,6 +235,7 @@ vc4_hvs_get_global_state(struct drm_atom
473 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
474 struct drm_atomic_state *state)
475 {
476 + struct vc4_hvs *hvs = vc4->hvs;
477 struct drm_crtc_state *crtc_state;
478 struct drm_crtc *crtc;
479 unsigned int i;
480 @@ -274,6 +276,7 @@ static void vc4_hvs_pv_muxing_commit(str
481 static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
482 struct drm_atomic_state *state)
483 {
484 + struct vc4_hvs *hvs = vc4->hvs;
485 struct drm_crtc_state *crtc_state;
486 struct drm_crtc *crtc;
487 unsigned char mux;
488 @@ -367,7 +370,7 @@ static void vc4_atomic_commit_tail(struc
489 continue;
490
491 vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
492 - vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
493 + vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel);
494 }
495
496 for (channel = 0; channel < HVS_NUM_CHANNELS; channel++) {
Staging tree of Linus Walleij