git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From de6e05097f7db066afb0ad4c88b730949f7b7749 Mon Sep 17 00:00:00 2001
   2 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   3 Date: Tue, 4 Apr 2023 18:21:35 +0100
   4 Subject: [PATCH] nvmem: mtk-efuse: Support postprocessing for GPU speed
   5  binning data
   6
   7 On some MediaTek SoCs GPU speed binning data is available for read
   8 in the SoC's eFuse array but it has a format that is incompatible
   9 with what the OPP API expects, as we read a number from 0 to 7 but
  10 opp-supported-hw is expecting a bitmask to enable an OPP entry:
  11 being what we read limited to 0-7, it's straightforward to simply
  12 convert the value to BIT(value) as a post-processing action.
  13
  14 So, introduce post-processing support and enable it by evaluating
  15 the newly introduced platform data's `uses_post_processing` member,
  16 currently enabled only for MT8186.
  17
  18 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  19 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
  20 Link: https://lore.kernel.org/r/20230404172148.82422-28-srinivas.kandagatla@linaro.org
  21 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  22 ---
  23  drivers/nvmem/mtk-efuse.c | 53 +++++++++++++++++++++++++++++++++++++--
  24  1 file changed, 51 insertions(+), 2 deletions(-)
  25
  26 --- a/drivers/nvmem/mtk-efuse.c
  27 +++ b/drivers/nvmem/mtk-efuse.c
  28 @@ -10,6 +10,11 @@
  29  #include <linux/io.h>
  30  #include <linux/nvmem-provider.h>
  31  #include <linux/platform_device.h>
  32 +#include <linux/property.h>
  33 +
  34 +struct mtk_efuse_pdata {
  35 +       bool uses_post_processing;
  36 +};
  37
  38  struct mtk_efuse_priv {
  39         void __iomem *base;
  40 @@ -29,6 +34,37 @@ static int mtk_reg_read(void *context,
  41         return 0;
  42  }
  43
  44 +static int mtk_efuse_gpu_speedbin_pp(void *context, const char *id, int index,
  45 +                                    unsigned int offset, void *data, size_t bytes)
  46 +{
  47 +       u8 *val = data;
  48 +
  49 +       if (val[0] < 8)
  50 +               val[0] = BIT(val[0]);
  51 +
  52 +       return 0;
  53 +}
  54 +
  55 +static void mtk_efuse_fixup_cell_info(struct nvmem_device *nvmem,
  56 +                                     struct nvmem_layout *layout,
  57 +                                     struct nvmem_cell_info *cell)
  58 +{
  59 +       size_t sz = strlen(cell->name);
  60 +
  61 +       /*
  62 +        * On some SoCs, the GPU speedbin is not read as bitmask but as
  63 +        * a number with range [0-7] (max 3 bits): post process to use
  64 +        * it in OPP tables to describe supported-hw.
  65 +        */
  66 +       if (cell->nbits <= 3 &&
  67 +           strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0)
  68 +               cell->read_post_process = mtk_efuse_gpu_speedbin_pp;
  69 +}
  70 +
  71 +static struct nvmem_layout mtk_efuse_layout = {
  72 +       .fixup_cell_info = mtk_efuse_fixup_cell_info,
  73 +};
  74 +
  75  static int mtk_efuse_probe(struct platform_device *pdev)
  76  {
  77         struct device *dev = &pdev->dev;
  78 @@ -36,6 +72,7 @@ static int mtk_efuse_probe(struct platfo
  79         struct nvmem_device *nvmem;
  80         struct nvmem_config econfig = {};
  81         struct mtk_efuse_priv *priv;
  82 +       const struct mtk_efuse_pdata *pdata;
  83
  84         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  85         if (!priv)
  86 @@ -45,20 +82,32 @@ static int mtk_efuse_probe(struct platfo
  87         if (IS_ERR(priv->base))
  88                 return PTR_ERR(priv->base);
  89
  90 +       pdata = device_get_match_data(dev);
  91         econfig.stride = 1;
  92         econfig.word_size = 1;
  93         econfig.reg_read = mtk_reg_read;
  94         econfig.size = resource_size(res);
  95         econfig.priv = priv;
  96         econfig.dev = dev;
  97 +       if (pdata->uses_post_processing)
  98 +               econfig.layout = &mtk_efuse_layout;
  99         nvmem = devm_nvmem_register(dev, &econfig);
 100
 101         return PTR_ERR_OR_ZERO(nvmem);
 102  }
 103
 104 +static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
 105 +       .uses_post_processing = true,
 106 +};
 107 +
 108 +static const struct mtk_efuse_pdata mtk_efuse_pdata = {
 109 +       .uses_post_processing = false,
 110 +};
 111 +
 112  static const struct of_device_id mtk_efuse_of_match[] = {
 113 -       { .compatible = "mediatek,mt8173-efuse",},
 114 -       { .compatible = "mediatek,efuse",},
 115 +       { .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
 116 +       { .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
 117 +       { .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },
 118         {/* sentinel */},
 119  };
 120  MODULE_DEVICE_TABLE(of, mtk_efuse_of_match);