git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 512ea2edfe15ffa2cd839b3a31d768145f2edc20 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Sat, 26 Feb 2022 14:52:27 +0100
   4 Subject: [PATCH 07/14] clk: qcom: gcc-ipq806x: add additional freq nss cores
   5
   6 Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
   7 clocked to 800MHz. Add these missing freq to the gcc driver.
   8 Set the freq_tbl for the ubi32_cores to the correct values based on the
   9 machine compatible.
  10
  11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  12 Reviewed-by: Stephen Boyd <sboyd@kernel.org>
  13 Tested-by: Jonathan McDowell <noodles@earth.li>
  14 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  15 Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com
  16 ---
  17  drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++---
  18  1 file changed, 21 insertions(+), 3 deletions(-)
  19
  20 --- a/drivers/clk/qcom/gcc-ipq806x.c
  21 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  22 @@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = {
  23
  24  static struct pll_freq_tbl pll18_freq_tbl[] = {
  25         NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
  26 +       NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
  27         NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
  28 +       NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
  29  };
  30
  31  static struct clk_pll pll18 = {
  32 @@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = {
  33         },
  34  };
  35
  36 -static const struct freq_tbl clk_tbl_nss[] = {
  37 +static const struct freq_tbl clk_tbl_nss_ipq8064[] = {
  38         { 110000000, P_PLL18, 1, 1, 5 },
  39         { 275000000, P_PLL18, 2, 0, 0 },
  40         { 550000000, P_PLL18, 1, 0, 0 },
  41 @@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss
  42         { }
  43  };
  44
  45 +static const struct freq_tbl clk_tbl_nss_ipq8065[] = {
  46 +       { 110000000, P_PLL18, 1, 1, 5 },
  47 +       { 275000000, P_PLL18, 2, 0, 0 },
  48 +       { 600000000, P_PLL18, 1, 0, 0 },
  49 +       { 800000000, P_PLL18, 1, 0, 0 },
  50 +       { }
  51 +};
  52 +
  53  static struct clk_dyn_rcg ubi32_core1_src_clk = {
  54         .ns_reg[0] = 0x3d2c,
  55         .ns_reg[1] = 0x3d30,
  56 @@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_sr
  57                 .pre_div_width = 2,
  58         },
  59         .mux_sel_bit = 0,
  60 -       .freq_tbl = clk_tbl_nss,
  61 +       /* nss freq table is selected based on the SoC compatible */
  62         .clkr = {
  63                 .enable_reg = 0x3d20,
  64                 .enable_mask = BIT(1),
  65 @@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_sr
  66                 .pre_div_width = 2,
  67         },
  68         .mux_sel_bit = 0,
  69 -       .freq_tbl = clk_tbl_nss,
  70 +       /* nss freq table is selected based on the SoC compatible */
  71         .clkr = {
  72                 .enable_reg = 0x3d40,
  73                 .enable_mask = BIT(1),
  74 @@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct plat
  75         if (ret)
  76                 return ret;
  77
  78 +       if (of_machine_is_compatible("qcom,ipq8065")) {
  79 +               ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
  80 +               ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
  81 +       } else {
  82 +               ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
  83 +               ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
  84 +       }
  85 +
  86         ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
  87         if (ret)
  88                 return ret;