git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 180ce25d5c3ccff206f084b7ab350778641d1b1c Mon Sep 17 00:00:00 2001
   2 From: Prasad Malisetty <pmaliset@codeaurora.org>
   3 Date: Thu, 7 Oct 2021 23:18:42 +0530
   4 Subject: [PATCH] PCI: qcom: Replace ops with struct pcie_cfg in pcie match
   5  data
   6
   7 Add struct qcom_pcie_cfg as match data for all platforms.  Assign
   8 appropriate platform ops into struct qcom_pcie_cfg and read using
   9 of_device_get_match_data() in qcom_pcie_probe().
  10
  11 Link: https://lore.kernel.org/r/1633628923-25047-5-git-send-email-pmaliset@codeaurora.org
  12 Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
  13 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  14 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  15 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
  16 ---
  17  drivers/pci/controller/dwc/pcie-qcom.c | 66 +++++++++++++++++++++-----
  18  1 file changed, 55 insertions(+), 11 deletions(-)
  19
  20 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  21 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  22 @@ -202,6 +202,10 @@ struct qcom_pcie_ops {
  23         int (*config_sid)(struct qcom_pcie *pcie);
  24  };
  25
  26 +struct qcom_pcie_cfg {
  27 +       const struct qcom_pcie_ops *ops;
  28 +};
  29 +
  30  struct qcom_pcie {
  31         struct dw_pcie *pci;
  32         void __iomem *parf;                     /* DT parf */
  33 @@ -1467,6 +1471,38 @@ static const struct qcom_pcie_ops ops_1_
  34         .config_sid = qcom_pcie_config_sid_sm8250,
  35  };
  36
  37 +static const struct qcom_pcie_cfg apq8084_cfg = {
  38 +       .ops = &ops_1_0_0,
  39 +};
  40 +
  41 +static const struct qcom_pcie_cfg ipq8064_cfg = {
  42 +       .ops = &ops_2_1_0,
  43 +};
  44 +
  45 +static const struct qcom_pcie_cfg msm8996_cfg = {
  46 +       .ops = &ops_2_3_2,
  47 +};
  48 +
  49 +static const struct qcom_pcie_cfg ipq8074_cfg = {
  50 +       .ops = &ops_2_3_3,
  51 +};
  52 +
  53 +static const struct qcom_pcie_cfg ipq4019_cfg = {
  54 +       .ops = &ops_2_4_0,
  55 +};
  56 +
  57 +static const struct qcom_pcie_cfg sdm845_cfg = {
  58 +       .ops = &ops_2_7_0,
  59 +};
  60 +
  61 +static const struct qcom_pcie_cfg sm8250_cfg = {
  62 +       .ops = &ops_1_9_0,
  63 +};
  64 +
  65 +static const struct qcom_pcie_cfg sc7280_cfg = {
  66 +       .ops = &ops_1_9_0,
  67 +};
  68 +
  69  static const struct dw_pcie_ops dw_pcie_ops = {
  70         .link_up = qcom_pcie_link_up,
  71         .start_link = qcom_pcie_start_link,
  72 @@ -1478,6 +1514,7 @@ static int qcom_pcie_probe(struct platfo
  73         struct pcie_port *pp;
  74         struct dw_pcie *pci;
  75         struct qcom_pcie *pcie;
  76 +       const struct qcom_pcie_cfg *pcie_cfg;
  77         int ret;
  78
  79         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
  80 @@ -1499,7 +1536,13 @@ static int qcom_pcie_probe(struct platfo
  81
  82         pcie->pci = pci;
  83
  84 -       pcie->ops = of_device_get_match_data(dev);
  85 +       pcie_cfg = of_device_get_match_data(dev);
  86 +       if (!pcie_cfg || !pcie_cfg->ops) {
  87 +               dev_err(dev, "Invalid platform data\n");
  88 +               return -EINVAL;
  89 +       }
  90 +
  91 +       pcie->ops = pcie_cfg->ops;
  92
  93         pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
  94         if (IS_ERR(pcie->reset)) {
  95 @@ -1555,16 +1598,17 @@ err_pm_runtime_put:
  96  }
  97
  98  static const struct of_device_id qcom_pcie_match[] = {
  99 -       { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
 100 -       { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
 101 -       { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
 102 -       { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
 103 -       { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
 104 -       { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
 105 -       { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
 106 -       { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
 107 -       { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
 108 -       { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
 109 +       { .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg },
 110 +       { .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg },
 111 +       { .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg },
 112 +       { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
 113 +       { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
 114 +       { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
 115 +       { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
 116 +       { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
 117 +       { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
 118 +       { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
 119 +       { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
 120         { }
 121  };
 122