b9a4cf7c21372d3c8b8473cc68d80d1949169cd1
[openwrt/staging/lynxis.git] /
1 From 5b8e6798e8f11bfc09f007d19776f0629e831828 Mon Sep 17 00:00:00 2001
2 From: Annaliese McDermond <nh6z@nh6z.net>
3 Date: Wed, 3 Apr 2019 21:01:55 -0700
4 Subject: [PATCH 414/782] ASoC: tlv320aic32x4: Add Playback PowerTune Controls
5
6 commit d3e6e374566e1154820a9a3dc82f7eef646fcf95 upstream.
7
8 PowerTune controls the power level of the chip. On playback this
9 indirectly controls things like the gain of the various output
10 amplifiers. This can allow for the decrease of output levels
11 from the codec. This adds controls for those power levels to
12 the driver.
13
14 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
15 Signed-off-by: Mark Brown <broonie@kernel.org>
16 ---
17 sound/soc/codecs/tlv320aic32x4.c | 9 +++++++++
18 sound/soc/codecs/tlv320aic32x4.h | 2 ++
19 2 files changed, 11 insertions(+)
20
21 --- a/sound/soc/codecs/tlv320aic32x4.c
22 +++ b/sound/soc/codecs/tlv320aic32x4.c
23 @@ -248,9 +248,18 @@ static const char * const lo_cm_text[] =
24
25 static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
26
27 +static const char * const ptm_text[] = {
28 + "P3", "P2", "P1",
29 +};
30 +
31 +static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
32 +static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
33 +
34 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
35 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
36 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
37 + SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
38 + SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
39 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
40 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
41 tlv_driver_gain),
42 --- a/sound/soc/codecs/tlv320aic32x4.h
43 +++ b/sound/soc/codecs/tlv320aic32x4.h
44 @@ -78,6 +78,8 @@ int aic32x4_register_clocks(struct devic
45
46 #define AIC32X4_PWRCFG AIC32X4_REG(1, 1)
47 #define AIC32X4_LDOCTL AIC32X4_REG(1, 2)
48 +#define AIC32X4_LPLAYBACK AIC32X4_REG(1, 3)
49 +#define AIC32X4_RPLAYBACK AIC32X4_REG(1, 4)
50 #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 9)
51 #define AIC32X4_CMMODE AIC32X4_REG(1, 10)
52 #define AIC32X4_HPLROUTE AIC32X4_REG(1, 12)