git.openwrt.org Git - openwrt/staging/thess.git/blob

   1 From 4869a146cd60fc8115230f0a45e15e534c531922 Mon Sep 17 00:00:00 2001
   2 From: Frank Sae <Frank.Sae@motor-comm.com>
   3 Date: Thu, 2 Feb 2023 11:00:34 +0800
   4 Subject: [PATCH] net: phy: Add BIT macro for Motorcomm yt8521/yt8531 gigabit
   5  ethernet phy
   6
   7 Add BIT macro for Motorcomm yt8521/yt8531 gigabit ethernet phy.
   8  This is a preparatory patch. Add BIT macro for 0xA012 reg, and
   9  supplement for 0xA001 and 0xA003 reg. These will be used to support dts.
  10
  11 Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
  12 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  13 Signed-off-by: David S. Miller <davem@davemloft.net>
  14 ---
  15  drivers/net/phy/motorcomm.c | 55 ++++++++++++++++++++++++++++++++++---
  16  1 file changed, 51 insertions(+), 4 deletions(-)
  17
  18 --- a/drivers/net/phy/motorcomm.c
  19 +++ b/drivers/net/phy/motorcomm.c
  20 @@ -161,6 +161,11 @@
  21
  22  #define YT8521_CHIP_CONFIG_REG                 0xA001
  23  #define YT8521_CCR_SW_RST                      BIT(15)
  24 +/* 1b0 disable 1.9ns rxc clock delay  *default*
  25 + * 1b1 enable 1.9ns rxc clock delay
  26 + */
  27 +#define YT8521_CCR_RXC_DLY_EN                  BIT(8)
  28 +#define YT8521_CCR_RXC_DLY_1_900_NS            1900
  29
  30  #define YT8521_CCR_MODE_SEL_MASK               (BIT(2) | BIT(1) | BIT(0))
  31  #define YT8521_CCR_MODE_UTP_TO_RGMII           0
  32 @@ -178,22 +183,41 @@
  33  #define YT8521_MODE_POLL                       0x3
  34
  35  #define YT8521_RGMII_CONFIG1_REG               0xA003
  36 -
  37 +/* 1b0 use original tx_clk_rgmii  *default*
  38 + * 1b1 use inverted tx_clk_rgmii.
  39 + */
  40 +#define YT8521_RC1R_TX_CLK_SEL_INVERTED                BIT(14)
  41  /* TX Gig-E Delay is bits 3:0, default 0x1
  42   * TX Fast-E Delay is bits 7:4, default 0xf
  43   * RX Delay is bits 13:10, default 0x0
  44   * Delay = 150ps * N
  45   * On = 2250ps, off = 0ps
  46   */
  47 -#define YT8521_RC1R_RX_DELAY_MASK              (0xF << 10)
  48 +#define YT8521_RC1R_RX_DELAY_MASK              GENMASK(13, 10)
  49  #define YT8521_RC1R_RX_DELAY_EN                        (0xF << 10)
  50  #define YT8521_RC1R_RX_DELAY_DIS               (0x0 << 10)
  51 -#define YT8521_RC1R_FE_TX_DELAY_MASK           (0xF << 4)
  52 +#define YT8521_RC1R_FE_TX_DELAY_MASK           GENMASK(7, 4)
  53  #define YT8521_RC1R_FE_TX_DELAY_EN             (0xF << 4)
  54  #define YT8521_RC1R_FE_TX_DELAY_DIS            (0x0 << 4)
  55 -#define YT8521_RC1R_GE_TX_DELAY_MASK           (0xF << 0)
  56 +#define YT8521_RC1R_GE_TX_DELAY_MASK           GENMASK(3, 0)
  57  #define YT8521_RC1R_GE_TX_DELAY_EN             (0xF << 0)
  58  #define YT8521_RC1R_GE_TX_DELAY_DIS            (0x0 << 0)
  59 +#define YT8521_RC1R_RGMII_0_000_NS             0
  60 +#define YT8521_RC1R_RGMII_0_150_NS             1
  61 +#define YT8521_RC1R_RGMII_0_300_NS             2
  62 +#define YT8521_RC1R_RGMII_0_450_NS             3
  63 +#define YT8521_RC1R_RGMII_0_600_NS             4
  64 +#define YT8521_RC1R_RGMII_0_750_NS             5
  65 +#define YT8521_RC1R_RGMII_0_900_NS             6
  66 +#define YT8521_RC1R_RGMII_1_050_NS             7
  67 +#define YT8521_RC1R_RGMII_1_200_NS             8
  68 +#define YT8521_RC1R_RGMII_1_350_NS             9
  69 +#define YT8521_RC1R_RGMII_1_500_NS             10
  70 +#define YT8521_RC1R_RGMII_1_650_NS             11
  71 +#define YT8521_RC1R_RGMII_1_800_NS             12
  72 +#define YT8521_RC1R_RGMII_1_950_NS             13
  73 +#define YT8521_RC1R_RGMII_2_100_NS             14
  74 +#define YT8521_RC1R_RGMII_2_250_NS             15
  75
  76  #define YTPHY_MISC_CONFIG_REG                  0xA006
  77  #define YTPHY_MCR_FIBER_SPEED_MASK             BIT(0)
  78 @@ -222,6 +246,29 @@
  79   */
  80  #define YTPHY_WCR_TYPE_PULSE                   BIT(0)
  81
  82 +#define YTPHY_SYNCE_CFG_REG                    0xA012
  83 +#define YT8521_SCR_SYNCE_ENABLE                        BIT(5)
  84 +/* 1b0 output 25m clock
  85 + * 1b1 output 125m clock  *default*
  86 + */
  87 +#define YT8521_SCR_CLK_FRE_SEL_125M            BIT(3)
  88 +#define YT8521_SCR_CLK_SRC_MASK                        GENMASK(2, 1)
  89 +#define YT8521_SCR_CLK_SRC_PLL_125M            0
  90 +#define YT8521_SCR_CLK_SRC_UTP_RX              1
  91 +#define YT8521_SCR_CLK_SRC_SDS_RX              2
  92 +#define YT8521_SCR_CLK_SRC_REF_25M             3
  93 +#define YT8531_SCR_SYNCE_ENABLE                        BIT(6)
  94 +/* 1b0 output 25m clock   *default*
  95 + * 1b1 output 125m clock
  96 + */
  97 +#define YT8531_SCR_CLK_FRE_SEL_125M            BIT(4)
  98 +#define YT8531_SCR_CLK_SRC_MASK                        GENMASK(3, 1)
  99 +#define YT8531_SCR_CLK_SRC_PLL_125M            0
 100 +#define YT8531_SCR_CLK_SRC_UTP_RX              1
 101 +#define YT8531_SCR_CLK_SRC_SDS_RX              2
 102 +#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL  3
 103 +#define YT8531_SCR_CLK_SRC_REF_25M             4
 104 +#define YT8531_SCR_CLK_SRC_SSC_25M             5
 105  #define YT8531S_SYNCE_CFG_REG                  0xA012
 106  #define YT8531S_SCR_SYNCE_ENABLE               BIT(6)
 107