git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From d568739f1c21e1768a887ff85611769f782eb64f Mon Sep 17 00:00:00 2001
   2 From: Baruch Siach <baruch.siach@siklu.com>
   3 Date: Tue, 21 Jun 2022 11:54:53 +0300
   4 Subject: [PATCH] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
   5
   6 The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
   7 PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
   8 describe its meaning.
   9
  10 Link: https://lore.kernel.org/r/3025d5e1d8da64798db6958f9780c4763fbcac47.1655799816.git.baruch@tkos.co.il
  11 Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  12 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  13 Reviewed-by: Rob Herring <robh@kernel.org>
  14 Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  15 ---
  16  drivers/pci/controller/dwc/pcie-qcom.c | 17 +++++++++++++++--
  17  1 file changed, 15 insertions(+), 2 deletions(-)
  18
  19 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  20 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  21 @@ -69,7 +69,20 @@
  22  #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1                0x81c
  23  #define CFG_BRIDGE_SB_INIT                     BIT(0)
  24
  25 -#define PCIE_CAP_LINK1_VAL                     0x2FD7F
  26 +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL          FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \
  27 +                                               250)
  28 +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE                FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \
  29 +                                               1)
  30 +#define PCIE_CAP_SLOT_VAL                      (PCI_EXP_SLTCAP_ABP | \
  31 +                                               PCI_EXP_SLTCAP_PCP | \
  32 +                                               PCI_EXP_SLTCAP_MRLSP | \
  33 +                                               PCI_EXP_SLTCAP_AIP | \
  34 +                                               PCI_EXP_SLTCAP_PIP | \
  35 +                                               PCI_EXP_SLTCAP_HPS | \
  36 +                                               PCI_EXP_SLTCAP_HPC | \
  37 +                                               PCI_EXP_SLTCAP_EIP | \
  38 +                                               PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
  39 +                                               PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
  40
  41  #define PCIE20_PARF_Q2A_FLUSH                  0x1AC
  42
  43 @@ -1125,7 +1138,7 @@ static int qcom_pcie_post_init_2_3_3(str
  44
  45         writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
  46         writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
  47 -       writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
  48 +       writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
  49
  50         val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
  51         val &= ~PCI_EXP_LNKCAP_ASPMS;