git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 7000a609473ffe14d32c656cdd0ff3ca0d3ecbd7 Mon Sep 17 00:00:00 2001
   2 From: Tianling Shen <cnsztl@gmail.com>
   3 Date: Tue, 11 Apr 2023 18:14:49 +0800
   4 Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
   5
   6 The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
   7 chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
   8
   9 The device tree is taken from the kernel linux-next branch:
  10 https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9
  11
  12 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
  13 Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
  14 ---
  15  arch/arm/dts/Makefile                      |   1 +
  16  arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi |   3 +
  17  arch/arm/dts/rk3328-nanopi-r2c.dts         |  40 ++++++++
  18  board/rockchip/evb_rk3328/MAINTAINERS      |   6 ++
  19  configs/nanopi-r2c-rk3328_defconfig        | 112 +++++++++++++++++++++
  20  5 files changed, 162 insertions(+)
  21  create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
  22  create mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts
  23  create mode 100644 configs/nanopi-r2c-rk3328_defconfig
  24
  25 --- a/arch/arm/dts/Makefile
  26 +++ b/arch/arm/dts/Makefile
  27 @@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
  28
  29  dtb-$(CONFIG_ROCKCHIP_RK3328) += \
  30         rk3328-evb.dtb \
  31 +       rk3328-nanopi-r2c.dtb \
  32         rk3328-nanopi-r2s.dtb \
  33         rk3328-roc-cc.dtb \
  34         rk3328-rock64.dtb \
  35 --- /dev/null
  36 +++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
  37 @@ -0,0 +1,3 @@
  38 +// SPDX-License-Identifier: GPL-2.0-or-later
  39 +
  40 +#include "rk3328-nanopi-r2s-u-boot.dtsi"
  41 --- /dev/null
  42 +++ b/arch/arm/dts/rk3328-nanopi-r2c.dts
  43 @@ -0,0 +1,40 @@
  44 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  45 +/*
  46 + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
  47 + * (http://www.friendlyarm.com)
  48 + *
  49 + * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
  50 + */
  51 +
  52 +/dts-v1/;
  53 +#include "rk3328-nanopi-r2s.dts"
  54 +
  55 +/ {
  56 +       model = "FriendlyElec NanoPi R2C";
  57 +       compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
  58 +};
  59 +
  60 +&gmac2io {
  61 +       phy-handle = <&yt8521s>;
  62 +       tx_delay = <0x22>;
  63 +       rx_delay = <0x12>;
  64 +
  65 +       mdio {
  66 +               /delete-node/ ethernet-phy@1;
  67 +
  68 +               yt8521s: ethernet-phy@3 {
  69 +                       compatible = "ethernet-phy-ieee802.3-c22";
  70 +                       reg = <3>;
  71 +
  72 +                       motorcomm,clk-out-frequency-hz = <125000000>;
  73 +                       motorcomm,keep-pll-enabled;
  74 +                       motorcomm,auto-sleep-disabled;
  75 +
  76 +                       pinctrl-0 = <&eth_phy_reset_pin>;
  77 +                       pinctrl-names = "default";
  78 +                       reset-assert-us = <10000>;
  79 +                       reset-deassert-us = <50000>;
  80 +                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
  81 +               };
  82 +       };
  83 +};
  84 --- a/board/rockchip/evb_rk3328/MAINTAINERS
  85 +++ b/board/rockchip/evb_rk3328/MAINTAINERS
  86 @@ -5,6 +5,12 @@ F:      board/rockchip/evb_rk3328
  87  F:      include/configs/evb_rk3328.h
  88  F:      configs/evb-rk3328_defconfig
  89
  90 +NANOPI-R2C-RK3328
  91 +M:      Tianling Shen <cnsztl@gmail.com>
  92 +S:      Maintained
  93 +F:      configs/nanopi-r2c-rk3328_defconfig
  94 +F:      arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
  95 +
  96  NANOPI-R2S-RK3328
  97  M:      David Bauer <mail@david-bauer.net>
  98  S:      Maintained
  99 --- /dev/null
 100 +++ b/configs/nanopi-r2c-rk3328_defconfig
 101 @@ -0,0 +1,98 @@
 102 +CONFIG_ARM=y
 103 +CONFIG_ARCH_ROCKCHIP=y
 104 +CONFIG_SYS_TEXT_BASE=0x00200000
 105 +CONFIG_SPL_GPIO_SUPPORT=y
 106 +CONFIG_NR_DRAM_BANKS=1
 107 +CONFIG_ENV_OFFSET=0x3F8000
 108 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
 109 +CONFIG_ROCKCHIP_RK3328=y
 110 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 111 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
 112 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
 113 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 114 +CONFIG_SPL_STACK_R_ADDR=0x600000
 115 +CONFIG_DEBUG_UART_BASE=0xFF130000
 116 +CONFIG_DEBUG_UART_CLOCK=24000000
 117 +CONFIG_DEBUG_UART=y
 118 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 119 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 120 +CONFIG_FIT=y
 121 +CONFIG_FIT_VERBOSE=y
 122 +CONFIG_SPL_LOAD_FIT=y
 123 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
 124 +# CONFIG_DISPLAY_CPUINFO is not set
 125 +CONFIG_DISPLAY_BOARDINFO_LATE=y
 126 +CONFIG_MISC_INIT_R=y
 127 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 128 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 129 +CONFIG_SPL_STACK_R=y
 130 +CONFIG_SPL_I2C_SUPPORT=y
 131 +CONFIG_SPL_POWER_SUPPORT=y
 132 +CONFIG_SPL_ATF=y
 133 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 134 +CONFIG_CMD_BOOTZ=y
 135 +CONFIG_CMD_GPT=y
 136 +CONFIG_CMD_MMC=y
 137 +CONFIG_CMD_USB=y
 138 +# CONFIG_CMD_SETEXPR is not set
 139 +CONFIG_CMD_TIME=y
 140 +CONFIG_SPL_OF_CONTROL=y
 141 +CONFIG_TPL_OF_CONTROL=y
 142 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 143 +CONFIG_TPL_OF_PLATDATA=y
 144 +CONFIG_ENV_IS_IN_MMC=y
 145 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 146 +CONFIG_NET_RANDOM_ETHADDR=y
 147 +CONFIG_TPL_DM=y
 148 +CONFIG_REGMAP=y
 149 +CONFIG_SPL_REGMAP=y
 150 +CONFIG_TPL_REGMAP=y
 151 +CONFIG_SYSCON=y
 152 +CONFIG_SPL_SYSCON=y
 153 +CONFIG_TPL_SYSCON=y
 154 +CONFIG_CLK=y
 155 +CONFIG_SPL_CLK=y
 156 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
 157 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 158 +CONFIG_ROCKCHIP_GPIO=y
 159 +CONFIG_SYS_I2C_ROCKCHIP=y
 160 +CONFIG_MMC_DW=y
 161 +CONFIG_MMC_DW_ROCKCHIP=y
 162 +CONFIG_SF_DEFAULT_SPEED=20000000
 163 +CONFIG_DM_ETH=y
 164 +CONFIG_ETH_DESIGNWARE=y
 165 +CONFIG_GMAC_ROCKCHIP=y
 166 +CONFIG_PINCTRL=y
 167 +CONFIG_SPL_PINCTRL=y
 168 +CONFIG_DM_PMIC=y
 169 +CONFIG_PMIC_RK8XX=y
 170 +CONFIG_SPL_DM_REGULATOR=y
 171 +CONFIG_REGULATOR_PWM=y
 172 +CONFIG_DM_REGULATOR_FIXED=y
 173 +CONFIG_SPL_DM_REGULATOR_FIXED=y
 174 +CONFIG_REGULATOR_RK8XX=y
 175 +CONFIG_PWM_ROCKCHIP=y
 176 +CONFIG_RAM=y
 177 +CONFIG_SPL_RAM=y
 178 +CONFIG_TPL_RAM=y
 179 +CONFIG_DM_RESET=y
 180 +CONFIG_BAUDRATE=1500000
 181 +CONFIG_DEBUG_UART_SHIFT=2
 182 +CONFIG_SYSINFO=y
 183 +CONFIG_SYSRESET=y
 184 +# CONFIG_TPL_SYSRESET is not set
 185 +CONFIG_USB=y
 186 +CONFIG_USB_XHCI_HCD=y
 187 +CONFIG_USB_XHCI_DWC3=y
 188 +CONFIG_USB_EHCI_HCD=y
 189 +CONFIG_USB_EHCI_GENERIC=y
 190 +CONFIG_USB_OHCI_HCD=y
 191 +CONFIG_USB_OHCI_GENERIC=y
 192 +CONFIG_USB_DWC2=y
 193 +CONFIG_USB_DWC3=y
 194 +# CONFIG_USB_DWC3_GADGET is not set
 195 +CONFIG_USB_GADGET=y
 196 +CONFIG_USB_GADGET_DWC2_OTG=y
 197 +CONFIG_SPL_TINY_MEMSET=y
 198 +CONFIG_TPL_TINY_MEMSET=y
 199 +CONFIG_ERRNO_STR=y