git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From e13c24ef2f068e651b9996922a08843d53513cab Mon Sep 17 00:00:00 2001
   2 From: Wen He <wen.he_1@nxp.com>
   3 Date: Fri, 20 Sep 2019 16:34:18 +0800
   4 Subject: [PATCH] arm64: dts: ls1028a: Update the clock providers for the Mali
   5  DP500
   6
   7 In order to maximise performance of the LCD Controller's 64-bit AXI
   8 bus, for any give speed bin of the device, the AXI master interface
   9 clock(ACLK) clock can be up to CPU_frequency/2, which is already
  10 capable of optimal performance. In general, ACLK is always expected
  11 to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and
  12 Main processing clock(PCLK) both are tied to the same clock as ACLK.
  13
  14 This change followed the LS1028A Architecture Specification Manual.
  15
  16 Signed-off-by: Wen He <wen.he_1@nxp.com>
  17 Acked-by: Li Yang <leoyang.li@nxp.com>
  18 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  19 ---
  20  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 17 ++---------------
  21  1 file changed, 2 insertions(+), 15 deletions(-)
  22
  23 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
  24 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
  25 @@ -90,20 +90,6 @@
  26                 clocks = <&osc_27m>;
  27         };
  28
  29 -       aclk: clock-axi {
  30 -               compatible = "fixed-clock";
  31 -               #clock-cells = <0>;
  32 -               clock-frequency = <650000000>;
  33 -               clock-output-names= "aclk";
  34 -       };
  35 -
  36 -       pclk: clock-apb {
  37 -               compatible = "fixed-clock";
  38 -               #clock-cells = <0>;
  39 -               clock-frequency = <650000000>;
  40 -               clock-output-names= "pclk";
  41 -       };
  42 -
  43         reboot {
  44                 compatible ="syscon-reboot";
  45                 regmap = <&rst>;
  46 @@ -880,7 +866,8 @@
  47                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
  48                              <0 223 IRQ_TYPE_LEVEL_HIGH>;
  49                 interrupt-names = "DE", "SE";
  50 -               clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>;
  51 +               clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>,
  52 +                        <&clockgen 2 2>;
  53                 clock-names = "pxlclk", "mclk", "aclk", "pclk";
  54                 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
  55                 arm,malidp-arqos-value = <0xd000d000>;