git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From fdbf35df9c091db9c46e57e9938e3f7a4f603a7c Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Thu, 14 Oct 2021 00:39:07 +0200
   4 Subject: dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties
   5
   6 Add names and descriptions of additional PORT0_PAD_CTRL properties.
   7 qca,sgmii-(rx|tx)clk-falling-edge are for setting the respective clock
   8 phase to failling edge.
   9
  10 Co-developed-by: Matthew Hagan <mnhagan88@gmail.com>
  11 Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
  12 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  13 Signed-off-by: David S. Miller <davem@davemloft.net>
  14 ---
  15  Documentation/devicetree/bindings/net/dsa/qca8k.txt | 4 ++++
  16  1 file changed, 4 insertions(+)
  17
  18 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
  19 +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
  20 @@ -37,6 +37,10 @@ A CPU port node has the following option
  21                            managed entity. See
  22                            Documentation/devicetree/bindings/net/fixed-link.txt
  23                            for details.
  24 +- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge.
  25 +                                Mostly used in qca8327 with CPU port 0 set to
  26 +                                sgmii.
  27 +- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.
  28
  29  For QCA8K the 'fixed-link' sub-node supports only the following properties:
  30