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bfa0df305345acb79b74bffd9b4ae4dc949add90
[openwrt/staging/blocktrron.git] /
1 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
2 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
3 @@ -96,12 +96,20 @@ static int set_mux_gmac2_gmac0_to_gephy(
4
5 static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)
6 {
7 - unsigned int val = 0;
8 + unsigned int val = 0, mask = 0, reg = 0;
9 bool updated = true;
10
11 switch (path) {
12 case MTK_ETH_PATH_GMAC2_SGMII:
13 - val = CO_QPHY_SEL;
14 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) {
15 + reg = USB_PHY_SWITCH_REG;
16 + val = SGMII_QPHY_SEL;
17 + mask = QPHY_SEL_MASK;
18 + } else {
19 + reg = INFRA_MISC2;
20 + val = CO_QPHY_SEL;
21 + mask = val;
22 + }
23 break;
24 default:
25 updated = false;
26 @@ -109,7 +117,7 @@ static int set_mux_u3_gmac2_to_qphy(stru
27 }
28
29 if (updated)
30 - regmap_update_bits(eth->infra, INFRA_MISC2, CO_QPHY_SEL, val);
31 + regmap_update_bits(eth->infra, reg, mask, val);
32
33 dev_dbg(eth->dev, "path %s in %s updated = %d\n",
34 mtk_eth_path_name(path), __func__, updated);
35 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
36 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
37 @@ -4757,6 +4757,26 @@ static const struct mtk_soc_data mt7629_
38 },
39 };
40
41 +static const struct mtk_soc_data mt7981_data = {
42 + .reg_map = &mt7986_reg_map,
43 + .ana_rgc3 = 0x128,
44 + .caps = MT7981_CAPS,
45 + .hw_features = MTK_HW_FEATURES,
46 + .required_clks = MT7981_CLKS_BITMAP,
47 + .required_pctl = false,
48 + .offload_version = 2,
49 + .hash_offset = 4,
50 + .foe_entry_size = sizeof(struct mtk_foe_entry),
51 + .txrx = {
52 + .txd_size = sizeof(struct mtk_tx_dma_v2),
53 + .rxd_size = sizeof(struct mtk_rx_dma_v2),
54 + .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
55 + .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
56 + .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
57 + .dma_len_offset = 8,
58 + },
59 +};
60 +
61 static const struct mtk_soc_data mt7986_data = {
62 .reg_map = &mt7986_reg_map,
63 .ana_rgc3 = 0x128,
64 @@ -4799,6 +4819,7 @@ const struct of_device_id of_mtk_match[]
65 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
66 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
67 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
68 + { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
69 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
70 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
71 {},
72 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
73 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
74 @@ -553,11 +553,22 @@
75 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
76 #define SGMII_PHYA_PWD BIT(4)
77
78 +/* Register to QPHY wrapper control */
79 +#define SGMSYS_QPHY_WRAP_CTRL 0xec
80 +#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
81 +#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
82 +#define MTK_SGMII_FLAG_PN_SWAP BIT(0)
83 +
84 /* Infrasys subsystem config registers */
85 #define INFRA_MISC2 0x70c
86 #define CO_QPHY_SEL BIT(0)
87 #define GEPHY_MAC_SEL BIT(1)
88
89 +/* Top misc registers */
90 +#define USB_PHY_SWITCH_REG 0x218
91 +#define QPHY_SEL_MASK GENMASK(1, 0)
92 +#define SGMII_QPHY_SEL 0x2
93 +
94 /* MT7628/88 specific stuff */
95 #define MT7628_PDMA_OFFSET 0x0800
96 #define MT7628_SDM_OFFSET 0x0c00
97 @@ -738,6 +749,17 @@ enum mtk_clks_map {
98 BIT(MTK_CLK_SGMII2_CDR_FB) | \
99 BIT(MTK_CLK_SGMII_CK) | \
100 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
101 +#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
102 + BIT(MTK_CLK_WOCPU0) | \
103 + BIT(MTK_CLK_SGMII_TX_250M) | \
104 + BIT(MTK_CLK_SGMII_RX_250M) | \
105 + BIT(MTK_CLK_SGMII_CDR_REF) | \
106 + BIT(MTK_CLK_SGMII_CDR_FB) | \
107 + BIT(MTK_CLK_SGMII2_TX_250M) | \
108 + BIT(MTK_CLK_SGMII2_RX_250M) | \
109 + BIT(MTK_CLK_SGMII2_CDR_REF) | \
110 + BIT(MTK_CLK_SGMII2_CDR_FB) | \
111 + BIT(MTK_CLK_SGMII_CK))
112 #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
113 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
114 BIT(MTK_CLK_SGMII_TX_250M) | \
115 @@ -851,6 +873,7 @@ enum mkt_eth_capabilities {
116 MTK_NETSYS_V2_BIT,
117 MTK_SOC_MT7628_BIT,
118 MTK_RSTCTRL_PPE1_BIT,
119 + MTK_U3_COPHY_V2_BIT,
120
121 /* MUX BITS*/
122 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
123 @@ -885,6 +908,7 @@ enum mkt_eth_capabilities {
124 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
125 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
126 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
127 +#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
128
129 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
130 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
131 @@ -963,6 +987,11 @@ enum mkt_eth_capabilities {
132 MTK_MUX_U3_GMAC2_TO_QPHY | \
133 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
134
135 +#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
136 + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
137 + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
138 + MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
139 +
140 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
141 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
142 MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
143 @@ -1076,12 +1105,14 @@ struct mtk_soc_data {
144 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
145 * @interface: Currently configured interface mode
146 * @pcs: Phylink PCS structure
147 + * @flags: Flags indicating hardware properties
148 */
149 struct mtk_pcs {
150 struct regmap *regmap;
151 u32 ana_rgc3;
152 phy_interface_t interface;
153 struct phylink_pcs pcs;
154 + u32 flags;
155 };
156
157 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its
158 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
159 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
160 @@ -87,6 +87,11 @@ static int mtk_pcs_config(struct phylink
161 regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
162 SGMII_PHYA_PWD, SGMII_PHYA_PWD);
163
164 + if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
165 + regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
166 + SGMII_PN_SWAP_MASK,
167 + SGMII_PN_SWAP_TX_RX);
168 +
169 /* Reset SGMII PCS state */
170 regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
171 SGMII_SW_RESET, SGMII_SW_RESET);
172 @@ -186,6 +191,11 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
173
174 ss->pcs[i].ana_rgc3 = ana_rgc3;
175 ss->pcs[i].regmap = syscon_node_to_regmap(np);
176 +
177 + ss->pcs[i].flags = 0;
178 + if (of_property_read_bool(np, "mediatek,pnswap"))
179 + ss->pcs[i].flags |= MTK_SGMII_FLAG_PN_SWAP;
180 +
181 of_node_put(np);
182 if (IS_ERR(ss->pcs[i].regmap))
183 return PTR_ERR(ss->pcs[i].regmap);
Staging tree of David Bauer