bfd6dbe0db8b36436927b98ae3b73d5ba24c3712
[openwrt/staging/jow.git] /
1 From 477ed3ade6a46e445b4e2348b710c51df4f6f4b1 Mon Sep 17 00:00:00 2001
2 From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
3 Date: Thu, 23 Feb 2023 19:29:29 +0530
4 Subject: [PATCH] arm64: dts: rockchip: Enable USB OTG for rk3566 Radxa CM3
5
6 Enable USB OTG support for Radxa Compute Module 3 IO Board
7
8 Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
9 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
10 Link: https://lore.kernel.org/r/20230223135929.630787-1-abbaraju.manojsai@amarulasolutions.com
11 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
12 ---
13 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 8 ++++++++
14 1 file changed, 8 insertions(+)
15
16 --- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
17 +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
18 @@ -254,6 +254,14 @@
19 status = "okay";
20 };
21
22 +&usb2phy0_otg {
23 + status = "okay";
24 +};
25 +
26 +&usb_host0_xhci {
27 + status = "okay";
28 +};
29 +
30 &vop {
31 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
32 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;