git.openwrt.org Git - openwrt/staging/thess.git/blob

   1 From cfbd6de588ef659c198083205dc954a6d3ed2aec Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Thu, 29 Dec 2022 17:33:35 +0100
   4 Subject: [PATCH 4/5] net: dsa: qca8k: introduce single mii read/write lo/hi
   5
   6 It may be useful to read/write just the lo or hi half of a reg.
   7
   8 This is especially useful for phy poll with the use of mdio master.
   9 The mdio master reg is composed by the first 16 bit related to setup and
  10 the other half with the returned data or data to write.
  11
  12 Refactor the mii function to permit single mii read/write of lo or hi
  13 half of the reg.
  14
  15 Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
  16 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  17 Signed-off-by: David S. Miller <davem@davemloft.net>
  18 ---
  19  drivers/net/dsa/qca/qca8k-8xxx.c | 106 ++++++++++++++++++++++++-------
  20  1 file changed, 84 insertions(+), 22 deletions(-)
  21
  22 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
  23 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
  24 @@ -37,42 +37,104 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
  25  }
  26
  27  static int
  28 -qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  29 +qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  30  {
  31         int ret;
  32 +       u16 lo;
  33
  34 -       ret = bus->read(bus, phy_id, regnum);
  35 -       if (ret >= 0) {
  36 -               *val = ret;
  37 -               ret = bus->read(bus, phy_id, regnum + 1);
  38 -               *val |= ret << 16;
  39 -       }
  40 +       lo = val & 0xffff;
  41 +       ret = bus->write(bus, phy_id, regnum, lo);
  42 +       if (ret < 0)
  43 +               dev_err_ratelimited(&bus->dev,
  44 +                                   "failed to write qca8k 32bit lo register\n");
  45 +
  46 +       return ret;
  47 +}
  48
  49 -       if (ret < 0) {
  50 +static int
  51 +qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  52 +{
  53 +       int ret;
  54 +       u16 hi;
  55 +
  56 +       hi = (u16)(val >> 16);
  57 +       ret = bus->write(bus, phy_id, regnum, hi);
  58 +       if (ret < 0)
  59                 dev_err_ratelimited(&bus->dev,
  60 -                                   "failed to read qca8k 32bit register\n");
  61 -               *val = 0;
  62 -               return ret;
  63 -       }
  64 +                                   "failed to write qca8k 32bit hi register\n");
  65
  66 +       return ret;
  67 +}
  68 +
  69 +static int
  70 +qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  71 +{
  72 +       int ret;
  73 +
  74 +       ret = bus->read(bus, phy_id, regnum);
  75 +       if (ret < 0)
  76 +               goto err;
  77 +
  78 +       *val = ret & 0xffff;
  79         return 0;
  80 +
  81 +err:
  82 +       dev_err_ratelimited(&bus->dev,
  83 +                           "failed to read qca8k 32bit lo register\n");
  84 +       *val = 0;
  85 +
  86 +       return ret;
  87  }
  88
  89 -static void
  90 -qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  91 +static int
  92 +qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  93  {
  94 -       u16 lo, hi;
  95         int ret;
  96
  97 -       lo = val & 0xffff;
  98 -       hi = (u16)(val >> 16);
  99 +       ret = bus->read(bus, phy_id, regnum);
 100 +       if (ret < 0)
 101 +               goto err;
 102
 103 -       ret = bus->write(bus, phy_id, regnum, lo);
 104 -       if (ret >= 0)
 105 -               ret = bus->write(bus, phy_id, regnum + 1, hi);
 106 +       *val = ret << 16;
 107 +       return 0;
 108 +
 109 +err:
 110 +       dev_err_ratelimited(&bus->dev,
 111 +                           "failed to read qca8k 32bit hi register\n");
 112 +       *val = 0;
 113 +
 114 +       return ret;
 115 +}
 116 +
 117 +static int
 118 +qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
 119 +{
 120 +       u32 hi, lo;
 121 +       int ret;
 122 +
 123 +       *val = 0;
 124 +
 125 +       ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo);
 126         if (ret < 0)
 127 -               dev_err_ratelimited(&bus->dev,
 128 -                                   "failed to write qca8k 32bit register\n");
 129 +               goto err;
 130 +
 131 +       ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi);
 132 +       if (ret < 0)
 133 +               goto err;
 134 +
 135 +       *val = lo | hi;
 136 +
 137 +err:
 138 +       return ret;
 139 +}
 140 +
 141 +static void
 142 +qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 143 +{
 144 +       if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0)
 145 +               return;
 146 +
 147 +       qca8k_mii_write_hi(bus, phy_id, regnum + 1, val);
 148  }
 149
 150  static int