git.openwrt.org Git - openwrt/staging/dedeckeh.git/blob

   1 From: Lorenzo Bianconi <lorenzo@kernel.org>
   2 Date: Fri, 20 May 2022 20:11:39 +0200
   3 Subject: [PATCH] net: ethernet: mtk_eth_soc: introduce support for mt7986
   4  chipset
   5
   6 Add support for mt7986-eth driver available on mt7986 soc.
   7
   8 Tested-by: Sam Shih <sam.shih@mediatek.com>
   9 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  10 Signed-off-by: David S. Miller <davem@davemloft.net>
  11 ---
  12
  13 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  14 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  15 @@ -87,6 +87,43 @@ static const struct mtk_reg_map mt7628_r
  16         },
  17  };
  18
  19 +static const struct mtk_reg_map mt7986_reg_map = {
  20 +       .tx_irq_mask            = 0x461c,
  21 +       .tx_irq_status          = 0x4618,
  22 +       .pdma = {
  23 +               .rx_ptr         = 0x6100,
  24 +               .rx_cnt_cfg     = 0x6104,
  25 +               .pcrx_ptr       = 0x6108,
  26 +               .glo_cfg        = 0x6204,
  27 +               .rst_idx        = 0x6208,
  28 +               .delay_irq      = 0x620c,
  29 +               .irq_status     = 0x6220,
  30 +               .irq_mask       = 0x6228,
  31 +               .int_grp        = 0x6250,
  32 +       },
  33 +       .qdma = {
  34 +               .qtx_cfg        = 0x4400,
  35 +               .rx_ptr         = 0x4500,
  36 +               .rx_cnt_cfg     = 0x4504,
  37 +               .qcrx_ptr       = 0x4508,
  38 +               .glo_cfg        = 0x4604,
  39 +               .rst_idx        = 0x4608,
  40 +               .delay_irq      = 0x460c,
  41 +               .fc_th          = 0x4610,
  42 +               .int_grp        = 0x4620,
  43 +               .hred           = 0x4644,
  44 +               .ctx_ptr        = 0x4700,
  45 +               .dtx_ptr        = 0x4704,
  46 +               .crx_ptr        = 0x4710,
  47 +               .drx_ptr        = 0x4714,
  48 +               .fq_head        = 0x4720,
  49 +               .fq_tail        = 0x4724,
  50 +               .fq_count       = 0x4728,
  51 +               .fq_blen        = 0x472c,
  52 +       },
  53 +       .gdm1_cnt               = 0x1c00,
  54 +};
  55 +
  56  /* strings used by ethtool */
  57  static const struct mtk_ethtool_stats {
  58         char str[ETH_GSTRING_LEN];
  59 @@ -110,7 +147,7 @@ static const char * const mtk_clks_sourc
  60         "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
  61         "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
  62         "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
  63 -       "sgmii_ck", "eth2pll",
  64 +       "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
  65  };
  66
  67  void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
  68 @@ -3711,6 +3748,21 @@ static const struct mtk_soc_data mt7629_
  69         },
  70  };
  71
  72 +static const struct mtk_soc_data mt7986_data = {
  73 +       .reg_map = &mt7986_reg_map,
  74 +       .ana_rgc3 = 0x128,
  75 +       .caps = MT7986_CAPS,
  76 +       .required_clks = MT7986_CLKS_BITMAP,
  77 +       .required_pctl = false,
  78 +       .txrx = {
  79 +               .txd_size = sizeof(struct mtk_tx_dma_v2),
  80 +               .rxd_size = sizeof(struct mtk_rx_dma_v2),
  81 +               .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
  82 +               .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
  83 +               .dma_len_offset = 8,
  84 +       },
  85 +};
  86 +
  87  static const struct mtk_soc_data rt5350_data = {
  88         .reg_map = &mt7628_reg_map,
  89         .caps = MT7628_CAPS,
  90 @@ -3733,6 +3785,7 @@ const struct of_device_id of_mtk_match[]
  91         { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
  92         { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
  93         { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
  94 +       { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
  95         { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
  96         {},
  97  };
  98 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  99 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 100 @@ -623,6 +623,10 @@ enum mtk_clks_map {
 101         MTK_CLK_SGMII2_CDR_FB,
 102         MTK_CLK_SGMII_CK,
 103         MTK_CLK_ETH2PLL,
 104 +       MTK_CLK_WOCPU0,
 105 +       MTK_CLK_WOCPU1,
 106 +       MTK_CLK_NETSYS0,
 107 +       MTK_CLK_NETSYS1,
 108         MTK_CLK_MAX
 109  };
 110
 111 @@ -653,6 +657,16 @@ enum mtk_clks_map {
 112                                  BIT(MTK_CLK_SGMII2_CDR_FB) | \
 113                                  BIT(MTK_CLK_SGMII_CK) | \
 114                                  BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
 115 +#define MT7986_CLKS_BITMAP     (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
 116 +                                BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
 117 +                                BIT(MTK_CLK_SGMII_TX_250M) | \
 118 +                                BIT(MTK_CLK_SGMII_RX_250M) | \
 119 +                                BIT(MTK_CLK_SGMII_CDR_REF) | \
 120 +                                BIT(MTK_CLK_SGMII_CDR_FB) | \
 121 +                                BIT(MTK_CLK_SGMII2_TX_250M) | \
 122 +                                BIT(MTK_CLK_SGMII2_RX_250M) | \
 123 +                                BIT(MTK_CLK_SGMII2_CDR_REF) | \
 124 +                                BIT(MTK_CLK_SGMII2_CDR_FB))
 125
 126  enum mtk_dev_state {
 127         MTK_HW_INIT,
 128 @@ -851,6 +865,10 @@ enum mkt_eth_capabilities {
 129                       MTK_MUX_U3_GMAC2_TO_QPHY | \
 130                       MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
 131
 132 +#define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
 133 +                     MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
 134 +                     MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
 135 +
 136  struct mtk_tx_dma_desc_info {
 137         dma_addr_t      addr;
 138         u32             size;