git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 542d455466bdf32e1bb70230ebcdefd8ed09643b Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 19 Jul 2023 17:17:22 +0800
   4 Subject: [PATCH 22/29] net: mediatek: add support for GMAC/USB3 PHY mux mode
   5  for MT7981
   6
   7 MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux
   8 register must be set to connect the SGMII phy to GMAC2.
   9
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 ---
  12  drivers/net/mtk_eth.c | 33 ++++++++++++++++++++++++++++++++-
  13  drivers/net/mtk_eth.h | 16 ++++++++++++++++
  14  2 files changed, 48 insertions(+), 1 deletion(-)
  15
  16 --- a/drivers/net/mtk_eth.c
  17 +++ b/drivers/net/mtk_eth.c
  18 @@ -103,6 +103,8 @@ struct mtk_eth_priv {
  19
  20         struct regmap *ethsys_regmap;
  21
  22 +       struct regmap *infra_regmap;
  23 +
  24         struct mii_dev *mdio_bus;
  25         int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
  26         int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
  27 @@ -186,6 +188,17 @@ static void mtk_ethsys_rmw(struct mtk_et
  28         regmap_write(priv->ethsys_regmap, reg, val);
  29  }
  30
  31 +static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
  32 +                         u32 set)
  33 +{
  34 +       uint val;
  35 +
  36 +       regmap_read(priv->infra_regmap, reg, &val);
  37 +       val &= ~clr;
  38 +       val |= set;
  39 +       regmap_write(priv->infra_regmap, reg, val);
  40 +}
  41 +
  42  /* Direct MDIO clause 22/45 access via SoC */
  43  static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
  44                       u32 cmd, u32 st)
  45 @@ -1139,6 +1152,11 @@ static void mtk_mac_init(struct mtk_eth_
  46                 break;
  47         case PHY_INTERFACE_MODE_SGMII:
  48         case PHY_INTERFACE_MODE_2500BASEX:
  49 +               if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
  50 +                       mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
  51 +                                     SGMII_QPHY_SEL);
  52 +               }
  53 +
  54                 ge_mode = GE_MODE_RGMII;
  55                 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
  56                                SYSCFG0_SGMII_SEL(priv->gmac_id));
  57 @@ -1497,6 +1515,19 @@ static int mtk_eth_of_to_plat(struct ude
  58         if (IS_ERR(priv->ethsys_regmap))
  59                 return PTR_ERR(priv->ethsys_regmap);
  60
  61 +       if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
  62 +               /* get corresponding infracfg phandle */
  63 +               ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
  64 +                                                NULL, 0, 0, &args);
  65 +
  66 +               if (ret)
  67 +                       return ret;
  68 +
  69 +               priv->infra_regmap = syscon_node_to_regmap(args.node);
  70 +               if (IS_ERR(priv->infra_regmap))
  71 +                       return PTR_ERR(priv->infra_regmap);
  72 +       }
  73 +
  74         /* Reset controllers */
  75         ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
  76         if (ret) {
  77 @@ -1614,7 +1645,7 @@ static const struct mtk_soc_data mt7986_
  78  };
  79
  80  static const struct mtk_soc_data mt7981_data = {
  81 -       .caps = MT7986_CAPS,
  82 +       .caps = MT7981_CAPS,
  83         .ana_rgc3 = 0x128,
  84         .pdma_base = PDMA_V2_BASE,
  85         .txd_size = sizeof(struct mtk_tx_dma_v2),
  86 --- a/drivers/net/mtk_eth.h
  87 +++ b/drivers/net/mtk_eth.h
  88 @@ -15,27 +15,38 @@
  89  enum mkt_eth_capabilities {
  90         MTK_TRGMII_BIT,
  91         MTK_TRGMII_MT7621_CLK_BIT,
  92 +       MTK_U3_COPHY_V2_BIT,
  93 +       MTK_INFRA_BIT,
  94         MTK_NETSYS_V2_BIT,
  95
  96         /* PATH BITS */
  97         MTK_ETH_PATH_GMAC1_TRGMII_BIT,
  98 +       MTK_ETH_PATH_GMAC2_SGMII_BIT,
  99  };
 100
 101  #define MTK_TRGMII                     BIT(MTK_TRGMII_BIT)
 102  #define MTK_TRGMII_MT7621_CLK          BIT(MTK_TRGMII_MT7621_CLK_BIT)
 103 +#define MTK_U3_COPHY_V2                        BIT(MTK_U3_COPHY_V2_BIT)
 104 +#define MTK_INFRA                      BIT(MTK_INFRA_BIT)
 105  #define MTK_NETSYS_V2                  BIT(MTK_NETSYS_V2_BIT)
 106
 107  /* Supported path present on SoCs */
 108  #define MTK_ETH_PATH_GMAC1_TRGMII      BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
 109
 110 +#define MTK_ETH_PATH_GMAC2_SGMII       BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
 111 +
 112  #define MTK_GMAC1_TRGMII       (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
 113
 114 +#define MTK_GMAC2_U3_QPHY      (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
 115 +
 116  #define MTK_HAS_CAPS(caps, _x)         (((caps) & (_x)) == (_x))
 117
 118  #define MT7621_CAPS  (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
 119
 120  #define MT7623_CAPS  (MTK_GMAC1_TRGMII)
 121
 122 +#define MT7981_CAPS  (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
 123 +
 124  #define MT7986_CAPS  (MTK_NETSYS_V2)
 125
 126  /* Frame Engine Register Bases */
 127 @@ -56,6 +67,11 @@ enum mkt_eth_capabilities {
 128  #define ETHSYS_CLKCFG0_REG             0x2c
 129  #define ETHSYS_TRGMII_CLK_SEL362_5     BIT(11)
 130
 131 +/* Top misc registers */
 132 +#define USB_PHY_SWITCH_REG             0x218
 133 +#define QPHY_SEL_MASK                  0x3
 134 +#define SGMII_QPHY_SEL                 0x2
 135 +
 136  /* SYSCFG0_GE_MODE: GE Modes */
 137  #define GE_MODE_RGMII                  0
 138  #define GE_MODE_MII                    1