git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 6c421a9c08286389bb331fe783e2625c9efcc187 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Thu, 7 Jul 2022 03:09:41 +0200
   4 Subject: [PATCH 7/8] ARM: dts: qcom: ipq8064: fix and add some missing gsbi
   5  node
   6
   7 Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing
   8 gsbi7 i2c node and gsbi1 node.
   9
  10 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  11 Tested-by: Jonathan McDowell <noodles@earth.li>
  12 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  13 Link: https://lore.kernel.org/r/20220707010943.20857-8-ansuelsmth@gmail.com
  14 ---
  15  arch/arm/boot/dts/qcom-ipq8064.dtsi | 54 ++++++++++++++++++++++++++++-
  16  1 file changed, 53 insertions(+), 1 deletion(-)
  17
  18 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  19 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  20 @@ -539,6 +539,44 @@
  21                         regulator;
  22                 };
  23
  24 +               gsbi1: gsbi@12440000 {
  25 +                       compatible = "qcom,gsbi-v1.0.0";
  26 +                       reg = <0x12440000 0x100>;
  27 +                       cell-index = <1>;
  28 +                       clocks = <&gcc GSBI1_H_CLK>;
  29 +                       clock-names = "iface";
  30 +                       #address-cells = <1>;
  31 +                       #size-cells = <1>;
  32 +                       ranges;
  33 +
  34 +                       syscon-tcsr = <&tcsr>;
  35 +
  36 +                       status = "disabled";
  37 +
  38 +                       gsbi1_serial: serial@12450000 {
  39 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  40 +                               reg = <0x12450000 0x100>,
  41 +                                     <0x12400000 0x03>;
  42 +                               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  43 +                               clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
  44 +                               clock-names = "core", "iface";
  45 +
  46 +                               status = "disabled";
  47 +                       };
  48 +
  49 +                       gsbi1_i2c: i2c@12460000 {
  50 +                               compatible = "qcom,i2c-qup-v1.1.1";
  51 +                               reg = <0x12460000 0x1000>;
  52 +                               interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  53 +                               clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
  54 +                               clock-names = "core", "iface";
  55 +                               #address-cells = <1>;
  56 +                               #size-cells = <0>;
  57 +
  58 +                               status = "disabled";
  59 +                       };
  60 +               };
  61 +
  62                 gsbi2: gsbi@12480000 {
  63                         compatible = "qcom,gsbi-v1.0.0";
  64                         cell-index = <2>;
  65 @@ -562,7 +600,7 @@
  66                                 status = "disabled";
  67                         };
  68
  69 -                       i2c@124a0000 {
  70 +                       gsbi2_i2c: i2c@124a0000 {
  71                                 compatible = "qcom,i2c-qup-v1.1.1";
  72                                 reg = <0x124a0000 0x1000>;
  73                                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
  74 @@ -727,6 +765,20 @@
  75                                 clock-names = "core", "iface";
  76                                 status = "disabled";
  77                         };
  78 +
  79 +                       gsbi7_i2c: i2c@16680000 {
  80 +                               compatible = "qcom,i2c-qup-v1.1.1";
  81 +                               reg = <0x16680000 0x1000>;
  82 +                               interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  83 +
  84 +                               clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
  85 +                               clock-names = "core", "iface";
  86 +
  87 +                               #address-cells = <1>;
  88 +                               #size-cells = <0>;
  89 +
  90 +                               status = "disabled";
  91 +                       };
  92                 };
  93
  94                 rng@1a500000 {