git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From d5841f8707dcb7a1f73607de67ab45dba93a56a4 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 29 Jul 2022 17:04:12 +0800
   4 Subject: [PATCH 55/71] board: mt7981: add reference board using new spi-nand
   5  driver
   6
   7 Add a new reference board using new spi-nand driver for SPI-NAND flash on
   8 SNFI interface
   9
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 ---
  12  arch/arm/dts/Makefile                  |   1 +
  13  arch/arm/dts/mt7981-snfi-nand-rfb.dts  | 132 +++++++++++++++++++++++++
  14  configs/mt7981_snfi_nand_rfb_defconfig |  57 +++++++++++
  15  3 files changed, 190 insertions(+)
  16  create mode 100644 arch/arm/dts/mt7981-snfi-nand-rfb.dts
  17  create mode 100644 configs/mt7981_snfi_nand_rfb_defconfig
  18
  19 --- a/arch/arm/dts/Makefile
  20 +++ b/arch/arm/dts/Makefile
  21 @@ -1308,6 +1308,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  22         mt7623n-bananapi-bpi-r2.dtb \
  23         mt7629-rfb.dtb \
  24         mt7981-rfb.dtb \
  25 +       mt7981-snfi-nand-rfb.dtb \
  26         mt7981-emmc-rfb.dtb \
  27         mt7981-sd-rfb.dtb \
  28         mt7986a-bpi-r3-sd.dtb \
  29 --- /dev/null
  30 +++ b/arch/arm/dts/mt7981-snfi-nand-rfb.dts
  31 @@ -0,0 +1,132 @@
  32 +// SPDX-License-Identifier: GPL-2.0
  33 +/*
  34 + * Copyright (c) 2021 MediaTek Inc.
  35 + * Author: Sam Shih <sam.shih@mediatek.com>
  36 + */
  37 +
  38 +/dts-v1/;
  39 +#include "mt7981.dtsi"
  40 +#include <dt-bindings/gpio/gpio.h>
  41 +
  42 +/ {
  43 +       #address-cells = <1>;
  44 +       #size-cells = <1>;
  45 +       model = "mt7981-rfb";
  46 +       compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
  47 +       chosen {
  48 +               stdout-path = &uart0;
  49 +               tick-timer = &timer0;
  50 +       };
  51 +};
  52 +
  53 +&uart0 {
  54 +       status = "okay";
  55 +};
  56 +
  57 +&uart1 {
  58 +       pinctrl-names = "default";
  59 +       pinctrl-0 = <&uart1_pins>;
  60 +       status = "disabled";
  61 +};
  62 +
  63 +&eth {
  64 +       status = "okay";
  65 +       mediatek,gmac-id = <0>;
  66 +       phy-mode = "sgmii";
  67 +       mediatek,switch = "mt7531";
  68 +       reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
  69 +
  70 +       fixed-link {
  71 +               speed = <1000>;
  72 +               full-duplex;
  73 +       };
  74 +};
  75 +
  76 +&pinctrl {
  77 +       snfi_pins: snfi-pins-func-1 {
  78 +               mux {
  79 +                       function = "flash";
  80 +                       groups = "snfi";
  81 +               };
  82 +
  83 +               clk {
  84 +                       pins = "SPI0_CLK";
  85 +                       drive-strength = <MTK_DRIVE_8mA>;
  86 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
  87 +               };
  88 +
  89 +               conf-pu {
  90 +                       pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
  91 +                       drive-strength = <MTK_DRIVE_6mA>;
  92 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
  93 +               };
  94 +
  95 +               conf-pd {
  96 +                       pins = "SPI0_MOSI", "SPI0_MISO";
  97 +                       drive-strength = <MTK_DRIVE_6mA>;
  98 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
  99 +               };
 100 +       };
 101 +
 102 +       spic_pins: spi1-pins-func-1 {
 103 +               mux {
 104 +                       function = "spi";
 105 +                       groups = "spi1_1";
 106 +               };
 107 +       };
 108 +
 109 +       uart1_pins: spi1-pins-func-3 {
 110 +               mux {
 111 +                       function = "uart";
 112 +                       groups = "uart1_2";
 113 +               };
 114 +       };
 115 +
 116 +       /* pin15 as pwm0 */
 117 +       one_pwm_pins: one-pwm-pins {
 118 +               mux {
 119 +                       function = "pwm";
 120 +                       groups = "pwm0_1";
 121 +               };
 122 +       };
 123 +
 124 +       /* pin15 as pwm0 and pin14 as pwm1 */
 125 +       two_pwm_pins: two-pwm-pins {
 126 +               mux {
 127 +                       function = "pwm";
 128 +                       groups = "pwm0_1", "pwm1_0";
 129 +               };
 130 +       };
 131 +
 132 +       /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
 133 +       three_pwm_pins: three-pwm-pins {
 134 +               mux {
 135 +                       function = "pwm";
 136 +                       groups = "pwm0_1", "pwm1_0", "pwm2";
 137 +               };
 138 +       };
 139 +
 140 +       mmc0_pins_default: mmc0default {
 141 +                mux {
 142 +                       function = "flash";
 143 +                       groups =  "emmc_45";
 144 +                 };
 145 +         };
 146 +};
 147 +
 148 +&snand {
 149 +       pinctrl-names = "default";
 150 +       pinctrl-0 = <&snfi_pins>;
 151 +       status = "okay";
 152 +       quad-spi;
 153 +};
 154 +
 155 +&pwm {
 156 +       pinctrl-names = "default";
 157 +       pinctrl-0 = <&two_pwm_pins>;
 158 +       status = "okay";
 159 +};
 160 +
 161 +&watchdog {
 162 +       status = "disabled";
 163 +};
 164 --- /dev/null
 165 +++ b/configs/mt7981_snfi_nand_rfb_defconfig
 166 @@ -0,0 +1,57 @@
 167 +CONFIG_ARM=y
 168 +CONFIG_POSITION_INDEPENDENT=y
 169 +CONFIG_ARCH_MEDIATEK=y
 170 +CONFIG_TEXT_BASE=0x41e00000
 171 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 172 +CONFIG_NR_DRAM_BANKS=1
 173 +CONFIG_ENV_SIZE=0x20000
 174 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb"
 175 +CONFIG_TARGET_MT7981=y
 176 +CONFIG_DEBUG_UART_BASE=0x11002000
 177 +CONFIG_DEBUG_UART_CLOCK=40000000
 178 +CONFIG_SYS_LOAD_ADDR=0x46000000
 179 +CONFIG_DEBUG_UART=y
 180 +# CONFIG_AUTOBOOT is not set
 181 +CONFIG_DEFAULT_FDT_FILE="mt7981-snfi-nand-rfb"
 182 +CONFIG_LOGLEVEL=7
 183 +CONFIG_LOG=y
 184 +CONFIG_SYS_PROMPT="MT7981> "
 185 +CONFIG_SYS_CBSIZE=512
 186 +CONFIG_SYS_PBSIZE=1049
 187 +# CONFIG_BOOTM_NETBSD is not set
 188 +# CONFIG_BOOTM_PLAN9 is not set
 189 +# CONFIG_BOOTM_RTEMS is not set
 190 +# CONFIG_BOOTM_VXWORKS is not set
 191 +# CONFIG_CMD_ELF is not set
 192 +# CONFIG_CMD_UNLZ4 is not set
 193 +# CONFIG_CMD_UNZIP is not set
 194 +CONFIG_CMD_GPIO=y
 195 +CONFIG_CMD_MTD=y
 196 +CONFIG_CMD_PING=y
 197 +CONFIG_CMD_SMC=y
 198 +CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0"
 199 +CONFIG_MTDPARTS_DEFAULT="spi-nand0:1024k(bl2),512k(u-boot-env),2048k(factory),2048k(fip),65536k(ubi)"
 200 +CONFIG_CMD_UBI=y
 201 +CONFIG_CMD_UBI_RENAME=y
 202 +CONFIG_ENV_OVERWRITE=y
 203 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 204 +CONFIG_NET_RANDOM_ETHADDR=y
 205 +CONFIG_REGMAP=y
 206 +CONFIG_SYSCON=y
 207 +CONFIG_CLK=y
 208 +# CONFIG_MMC is not set
 209 +CONFIG_MTD=y
 210 +CONFIG_DM_MTD=y
 211 +CONFIG_MTK_SPI_NAND=y
 212 +CONFIG_MTK_SPI_NAND_MTD=y
 213 +CONFIG_PHY_FIXED=y
 214 +CONFIG_DM_ETH=y
 215 +CONFIG_MEDIATEK_ETH=y
 216 +CONFIG_PINCTRL=y
 217 +CONFIG_PINCONF=y
 218 +CONFIG_PINCTRL_MT7981=y
 219 +CONFIG_POWER_DOMAIN=y
 220 +CONFIG_MTK_POWER_DOMAIN=y
 221 +CONFIG_DM_SERIAL=y
 222 +CONFIG_MTK_SERIAL=y
 223 +CONFIG_HEXDUMP=y