git.openwrt.org Git - openwrt/staging/neocturne.git/blob

   1 From: Lorenzo Bianconi <lorenzo@kernel.org>
   2 Date: Sat, 14 Jan 2023 18:01:28 +0100
   3 Subject: [PATCH] net: ethernet: mtk_eth_soc: introduce mtk_hw_reset utility
   4  routine
   5
   6 This is a preliminary patch to add Wireless Ethernet Dispatcher reset
   7 support.
   8
   9 Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
  10 Tested-by: Daniel Golle <daniel@makrotopia.org>
  11 Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
  12 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
  13 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  14 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  15 ---
  16
  17 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  18 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  19 @@ -3254,6 +3254,27 @@ static void mtk_set_mcr_max_rx(struct mt
  20                 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
  21  }
  22
  23 +static void mtk_hw_reset(struct mtk_eth *eth)
  24 +{
  25 +       u32 val;
  26 +
  27 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  28 +               regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
  29 +               val = RSTCTRL_PPE0_V2;
  30 +       } else {
  31 +               val = RSTCTRL_PPE0;
  32 +       }
  33 +
  34 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  35 +               val |= RSTCTRL_PPE1;
  36 +
  37 +       ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
  38 +
  39 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
  40 +               regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  41 +                            0x3ffffff);
  42 +}
  43 +
  44  static int mtk_hw_init(struct mtk_eth *eth)
  45  {
  46         u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
  47 @@ -3293,22 +3314,9 @@ static int mtk_hw_init(struct mtk_eth *e
  48                 return 0;
  49         }
  50
  51 -       if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  52 -               regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
  53 -               val = RSTCTRL_PPE0_V2;
  54 -       } else {
  55 -               val = RSTCTRL_PPE0;
  56 -       }
  57 -
  58 -       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  59 -               val |= RSTCTRL_PPE1;
  60 -
  61 -       ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
  62 +       mtk_hw_reset(eth);
  63
  64         if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  65 -               regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  66 -                            0x3ffffff);
  67 -
  68                 /* Set FE to PDMAv2 if necessary */
  69                 val = mtk_r32(eth, MTK_FE_GLO_MISC);
  70                 mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);