git.openwrt.org Git - openwrt/staging/dedeckeh.git/blob

   1 From a77b8f6d9aa90f80090e505d823a6dcf6b877136 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 31 Aug 2022 19:04:40 +0800
   4 Subject: [PATCH 14/32] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs
   5
   6 This patch add general-purpose timer support for MediaTek MT7981/MT7986.
   7 These two SoCs uses a newer version of timer with its register definition
   8 slightly changed.
   9
  10 Reviewed-by: Simon Glass <sjg@chromium.org>
  11 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  12 ---
  13  drivers/timer/mtk_timer.c | 59 ++++++++++++++++++++++++---------------
  14  1 file changed, 37 insertions(+), 22 deletions(-)
  15
  16 --- a/drivers/timer/mtk_timer.c
  17 +++ b/drivers/timer/mtk_timer.c
  18 @@ -13,24 +13,32 @@
  19  #include <asm/io.h>
  20  #include <linux/bitops.h>
  21
  22 -#define MTK_GPT4_CTRL  0x40
  23 -#define MTK_GPT4_CLK   0x44
  24 -#define MTK_GPT4_CNT   0x48
  25 -
  26 -#define GPT4_ENABLE    BIT(0)
  27 -#define GPT4_CLEAR     BIT(1)
  28 -#define GPT4_FREERUN   GENMASK(5, 4)
  29 -#define GPT4_CLK_SYS   0x0
  30 -#define GPT4_CLK_DIV1  0x0
  31 +#define MTK_GPT4_OFFSET_V1     0x40
  32 +#define MTK_GPT4_OFFSET_V2     0x80
  33 +
  34 +#define MTK_GPT_CON            0x0
  35 +#define MTK_GPT_V1_CLK         0x4
  36 +#define MTK_GPT_CNT            0x8
  37 +
  38 +#define GPT_ENABLE             BIT(0)
  39 +#define GPT_CLEAR              BIT(1)
  40 +#define GPT_V1_FREERUN         GENMASK(5, 4)
  41 +#define GPT_V2_FREERUN         GENMASK(6, 5)
  42 +
  43 +enum mtk_gpt_ver {
  44 +       MTK_GPT_V1,
  45 +       MTK_GPT_V2
  46 +};
  47
  48  struct mtk_timer_priv {
  49         void __iomem *base;
  50 +       unsigned int gpt4_offset;
  51  };
  52
  53  static u64 mtk_timer_get_count(struct udevice *dev)
  54  {
  55         struct mtk_timer_priv *priv = dev_get_priv(dev);
  56 -       u32 val = readl(priv->base + MTK_GPT4_CNT);
  57 +       u32 val = readl(priv->base + priv->gpt4_offset + MTK_GPT_CNT);
  58
  59         return timer_conv_64(val);
  60  }
  61 @@ -40,12 +48,27 @@ static int mtk_timer_probe(struct udevic
  62         struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  63         struct mtk_timer_priv *priv = dev_get_priv(dev);
  64         struct clk clk, parent;
  65 -       int ret;
  66 +       int ret, gpt_ver;
  67
  68         priv->base = dev_read_addr_ptr(dev);
  69 +       gpt_ver = dev_get_driver_data(dev);
  70 +
  71         if (!priv->base)
  72                 return -ENOENT;
  73
  74 +       if (gpt_ver == MTK_GPT_V2) {
  75 +               priv->gpt4_offset = MTK_GPT4_OFFSET_V2;
  76 +
  77 +               writel(GPT_V2_FREERUN | GPT_CLEAR | GPT_ENABLE,
  78 +                      priv->base + priv->gpt4_offset + MTK_GPT_CON);
  79 +       } else {
  80 +               priv->gpt4_offset = MTK_GPT4_OFFSET_V1;
  81 +
  82 +               writel(GPT_V1_FREERUN | GPT_CLEAR | GPT_ENABLE,
  83 +                      priv->base + priv->gpt4_offset + MTK_GPT_CON);
  84 +               writel(0, priv->base + priv->gpt4_offset + MTK_GPT_V1_CLK);
  85 +       }
  86 +
  87         ret = clk_get_by_index(dev, 0, &clk);
  88         if (ret)
  89                 return ret;
  90 @@ -61,16 +84,6 @@ static int mtk_timer_probe(struct udevic
  91         if (!uc_priv->clock_rate)
  92                 return -EINVAL;
  93
  94 -       /*
  95 -        * Initialize the timer:
  96 -        * 1. set clock source to system clock with clock divider setting to 1
  97 -        * 2. set timer mode to free running
  98 -        * 3. reset timer counter to 0 then enable the timer
  99 -        */
 100 -       writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK);
 101 -       writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE,
 102 -              priv->base + MTK_GPT4_CTRL);
 103 -
 104         return 0;
 105  }
 106
 107 @@ -79,8 +92,10 @@ static const struct timer_ops mtk_timer_
 108  };
 109
 110  static const struct udevice_id mtk_timer_ids[] = {
 111 -       { .compatible = "mediatek,timer" },
 112 -       { .compatible = "mediatek,mt6577-timer" },
 113 +       { .compatible = "mediatek,timer", .data = MTK_GPT_V1 },
 114 +       { .compatible = "mediatek,mt6577-timer", .data = MTK_GPT_V1 },
 115 +       { .compatible = "mediatek,mt7981-timer", .data = MTK_GPT_V2 },
 116 +       { .compatible = "mediatek,mt7986-timer", .data = MTK_GPT_V2 },
 117         { }
 118  };
 119