1 From a018800db986d63cf95b0779ebb33b5e246072a7 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Thu, 28 Jul 2022 10:01:00 +0800
4 Subject: [PATCH 21/31] pinctrl: mediatek: add pinctrl driver for MT7986 SoC
6 This patch adds pinctrl and gpio support for MT7986 SoC
8 Reviewed-by: Simon Glass <sjg@chromium.org>
9 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
11 drivers/pinctrl/mediatek/Kconfig | 4 +
12 drivers/pinctrl/mediatek/Makefile | 1 +
13 drivers/pinctrl/mediatek/pinctrl-mt7986.c | 775 ++++++++++++++++++++++
14 3 files changed, 780 insertions(+)
15 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c
17 --- a/drivers/pinctrl/mediatek/Kconfig
18 +++ b/drivers/pinctrl/mediatek/Kconfig
19 @@ -20,6 +20,10 @@ config PINCTRL_MT7981
20 bool "MT7981 SoC pinctrl driver"
23 +config PINCTRL_MT7986
24 + bool "MT7986 SoC pinctrl driver"
28 bool "MT8512 SoC pinctrl driver"
30 --- a/drivers/pinctrl/mediatek/Makefile
31 +++ b/drivers/pinctrl/mediatek/Makefile
32 @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-
33 obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
34 obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
35 obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
36 +obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
37 obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
38 obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
39 obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
41 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
43 +// SPDX-License-Identifier: GPL-2.0
45 + * The MT7986 driver based on Linux generic pinctrl binding.
47 + * Copyright (C) 2022 MediaTek Inc.
48 + * Author: Sam Shih <sam.shih@mediatek.com>
52 +#include "pinctrl-mtk-common.h"
54 +#define MT7986_TYPE0_PIN(_number, _name) \
55 + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
57 +#define MT7986_TYPE1_PIN(_number, _name) \
58 + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
60 +#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
61 + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \
62 + _s_bit, _x_bits, 32, 0)
64 +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
66 + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
70 + * enum - Locking variants of the iocfg bases
72 + * MT7986 have multiple bases to program pin configuration listed as the below:
73 + * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
74 + * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
75 + * _i_based could be used to indicate what base the pin should be mapped into.
77 + * Each iocfg register base control different group of pads on the SoC
83 + * +------------------------+
84 + * 8 | o o o o o o o o |
85 + * 7 | o o o o o o o o |
86 + * 6 | o o o o o o o o |
87 + * 5 | o o o o o o o o |
88 + * 4 | o o o o o o o o |
89 + * 3 | o o o o o o o o |
90 + * 2 | o o o o o o o o |
91 + * 1 | o o o o o o o o |
92 + * +------------------------+
94 + * inside Chip carrier
97 + * +------------------------+
100 + * 6 | +---------+ |
104 + * 2 | +---------+ |
106 + * +------------------------+
120 +static const char *const mt7986_pinctrl_register_base_names[] = {
121 + "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr",
125 +static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
126 + PIN_FIELD_GPIO(0, 100, 0x300, 0x10, 0, 4),
129 +static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
130 + PIN_FIELD_GPIO(0, 100, 0x0, 0x10, 0, 1),
133 +static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
134 + PIN_FIELD_GPIO(0, 100, 0x200, 0x10, 0, 1),
137 +static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
138 + PIN_FIELD_GPIO(0, 100, 0x100, 0x10, 0, 1),
141 +static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
142 + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
143 + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
144 + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
145 + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
146 + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
147 + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
148 + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
149 + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
150 + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
151 + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
152 + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
153 + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
154 + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
155 + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
156 + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
157 + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
158 + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
159 + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
160 + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
161 + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
162 + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
163 + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
164 + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
165 + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
166 + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
167 + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
168 + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
169 + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
170 + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
171 + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
172 + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
173 + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
174 + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
175 + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
176 + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
177 + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
178 + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
179 + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
180 + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
181 + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
182 + PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
183 + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
184 + PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
185 + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
186 + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
187 + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
188 + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
189 + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
190 + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
191 + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
192 + PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
195 +static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = {
196 + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
197 + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
198 + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
199 + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
200 + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
201 + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
202 + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
203 + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
204 + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
205 + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
206 + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
207 + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
208 + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
209 + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
210 + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
211 + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
212 + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
213 + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
214 + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
215 + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
216 + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
217 + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
218 + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
219 + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
220 + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
221 + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
222 + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
223 + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
224 + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
225 + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
226 + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
227 + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
228 + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
229 + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
230 + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
231 + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
232 + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
233 + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
234 + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
235 + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
236 + PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
237 + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
238 + PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
239 + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
240 + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
241 + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
242 + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
243 + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
244 + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
245 + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
246 + PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
249 +static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
250 + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
251 + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
252 + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
253 + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
254 + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
255 + PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
256 + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
257 + PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
258 + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
259 + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
260 + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
261 + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
262 + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
263 + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
264 + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
265 + PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
268 +static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
269 + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
270 + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
271 + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
272 + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
273 + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
274 + PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
275 + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
276 + PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
277 + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
278 + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
279 + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
280 + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
281 + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
282 + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
283 + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
284 + PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
287 +static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = {
288 + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
289 + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
290 + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
291 + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
292 + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
293 + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
294 + PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
295 + PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
296 + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
297 + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
298 + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
299 + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
300 + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
301 + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
302 + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
303 + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
304 + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
305 + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
306 + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
307 + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
308 + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
309 + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
310 + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
311 + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
312 + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
313 + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
314 + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
315 + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
316 + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
317 + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
318 + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
319 + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
320 + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
321 + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
322 + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
323 + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
324 + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
325 + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
326 + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
327 + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
328 + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
329 + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
330 + PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
331 + PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
332 + PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
333 + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
334 + PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
335 + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
336 + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
337 + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
338 + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
339 + PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
340 + PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
341 + PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
342 + PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
343 + PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
346 +static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = {
347 + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
348 + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
349 + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
350 + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
351 + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
352 + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
353 + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
354 + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
355 + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
356 + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
357 + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
358 + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
359 + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
360 + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
361 + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
362 + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
363 + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
364 + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
365 + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
366 + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
367 + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
368 + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
369 + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
370 + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
371 + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
372 + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
373 + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
374 + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
375 + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
376 + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
377 + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
378 + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
379 + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
380 + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
381 + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
384 +static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = {
385 + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
386 + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
387 + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
388 + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
389 + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
390 + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
391 + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
392 + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
393 + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
394 + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
395 + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
396 + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
397 + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
398 + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
399 + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
400 + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
401 + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
402 + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
403 + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
404 + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
405 + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
406 + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
407 + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
408 + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
409 + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
410 + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
411 + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
412 + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
413 + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
414 + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
415 + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
416 + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
417 + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
418 + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
419 + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
422 +static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
423 + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
424 + PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
425 + PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
426 + PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
427 + PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
428 + PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
429 + PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
430 + PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
431 + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
432 + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
433 + PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
434 + PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
435 + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
436 + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
437 + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
438 + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
439 + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
440 + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
441 + PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
442 + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
443 + PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
444 + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
445 + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
446 + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
447 + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
448 + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
449 + PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
450 + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
451 + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
452 + PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
453 + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
454 + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
455 + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
456 + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
457 + PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
460 +static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
461 + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
462 + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
463 + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
464 + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range),
465 + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range),
466 + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range),
467 + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range),
468 + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
469 + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
470 + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range),
471 + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range),
472 + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range),
475 +static const struct mtk_pin_desc mt7986_pins[] = {
476 + MT7986_TYPE0_PIN(0, "SYS_WATCHDOG"),
477 + MT7986_TYPE0_PIN(1, "WF2G_LED"),
478 + MT7986_TYPE0_PIN(2, "WF5G_LED"),
479 + MT7986_TYPE0_PIN(3, "I2C_SCL"),
480 + MT7986_TYPE0_PIN(4, "I2C_SDA"),
481 + MT7986_TYPE0_PIN(5, "GPIO_0"),
482 + MT7986_TYPE0_PIN(6, "GPIO_1"),
483 + MT7986_TYPE0_PIN(7, "GPIO_2"),
484 + MT7986_TYPE0_PIN(8, "GPIO_3"),
485 + MT7986_TYPE0_PIN(9, "GPIO_4"),
486 + MT7986_TYPE0_PIN(10, "GPIO_5"),
487 + MT7986_TYPE0_PIN(11, "GPIO_6"),
488 + MT7986_TYPE0_PIN(12, "GPIO_7"),
489 + MT7986_TYPE0_PIN(13, "GPIO_8"),
490 + MT7986_TYPE0_PIN(14, "GPIO_9"),
491 + MT7986_TYPE0_PIN(15, "GPIO_10"),
492 + MT7986_TYPE0_PIN(16, "GPIO_11"),
493 + MT7986_TYPE0_PIN(17, "GPIO_12"),
494 + MT7986_TYPE0_PIN(18, "GPIO_13"),
495 + MT7986_TYPE0_PIN(19, "GPIO_14"),
496 + MT7986_TYPE0_PIN(20, "GPIO_15"),
497 + MT7986_TYPE0_PIN(21, "PWM0"),
498 + MT7986_TYPE0_PIN(22, "PWM1"),
499 + MT7986_TYPE0_PIN(23, "SPI0_CLK"),
500 + MT7986_TYPE0_PIN(24, "SPI0_MOSI"),
501 + MT7986_TYPE0_PIN(25, "SPI0_MISO"),
502 + MT7986_TYPE0_PIN(26, "SPI0_CS"),
503 + MT7986_TYPE0_PIN(27, "SPI0_HOLD"),
504 + MT7986_TYPE0_PIN(28, "SPI0_WP"),
505 + MT7986_TYPE0_PIN(29, "SPI1_CLK"),
506 + MT7986_TYPE0_PIN(30, "SPI1_MOSI"),
507 + MT7986_TYPE0_PIN(31, "SPI1_MISO"),
508 + MT7986_TYPE0_PIN(32, "SPI1_CS"),
509 + MT7986_TYPE0_PIN(33, "SPI2_CLK"),
510 + MT7986_TYPE0_PIN(34, "SPI2_MOSI"),
511 + MT7986_TYPE0_PIN(35, "SPI2_MISO"),
512 + MT7986_TYPE0_PIN(36, "SPI2_CS"),
513 + MT7986_TYPE0_PIN(37, "SPI2_HOLD"),
514 + MT7986_TYPE0_PIN(38, "SPI2_WP"),
515 + MT7986_TYPE0_PIN(39, "UART0_RXD"),
516 + MT7986_TYPE0_PIN(40, "UART0_TXD"),
517 + MT7986_TYPE0_PIN(41, "PCIE_PERESET_N"),
518 + MT7986_TYPE0_PIN(42, "UART1_RXD"),
519 + MT7986_TYPE0_PIN(43, "UART1_TXD"),
520 + MT7986_TYPE0_PIN(44, "UART1_CTS"),
521 + MT7986_TYPE0_PIN(45, "UART1_RTS"),
522 + MT7986_TYPE0_PIN(46, "UART2_RXD"),
523 + MT7986_TYPE0_PIN(47, "UART2_TXD"),
524 + MT7986_TYPE0_PIN(48, "UART2_CTS"),
525 + MT7986_TYPE0_PIN(49, "UART2_RTS"),
526 + MT7986_TYPE0_PIN(50, "EMMC_DATA_0"),
527 + MT7986_TYPE0_PIN(51, "EMMC_DATA_1"),
528 + MT7986_TYPE0_PIN(52, "EMMC_DATA_2"),
529 + MT7986_TYPE0_PIN(53, "EMMC_DATA_3"),
530 + MT7986_TYPE0_PIN(54, "EMMC_DATA_4"),
531 + MT7986_TYPE0_PIN(55, "EMMC_DATA_5"),
532 + MT7986_TYPE0_PIN(56, "EMMC_DATA_6"),
533 + MT7986_TYPE0_PIN(57, "EMMC_DATA_7"),
534 + MT7986_TYPE0_PIN(58, "EMMC_CMD"),
535 + MT7986_TYPE0_PIN(59, "EMMC_CK"),
536 + MT7986_TYPE0_PIN(60, "EMMC_DSL"),
537 + MT7986_TYPE0_PIN(61, "EMMC_RSTB"),
538 + MT7986_TYPE0_PIN(62, "PCM_DTX"),
539 + MT7986_TYPE0_PIN(63, "PCM_DRX"),
540 + MT7986_TYPE0_PIN(64, "PCM_CLK"),
541 + MT7986_TYPE0_PIN(65, "PCM_FS"),
542 + MT7986_TYPE0_PIN(66, "MT7531_INT"),
543 + MT7986_TYPE0_PIN(67, "SMI_MDC"),
544 + MT7986_TYPE0_PIN(68, "SMI_MDIO"),
545 + MT7986_TYPE1_PIN(69, "WF0_DIG_RESETB"),
546 + MT7986_TYPE1_PIN(70, "WF0_CBA_RESETB"),
547 + MT7986_TYPE1_PIN(71, "WF0_XO_REQ"),
548 + MT7986_TYPE1_PIN(72, "WF0_TOP_CLK"),
549 + MT7986_TYPE1_PIN(73, "WF0_TOP_DATA"),
550 + MT7986_TYPE1_PIN(74, "WF0_HB1"),
551 + MT7986_TYPE1_PIN(75, "WF0_HB2"),
552 + MT7986_TYPE1_PIN(76, "WF0_HB3"),
553 + MT7986_TYPE1_PIN(77, "WF0_HB4"),
554 + MT7986_TYPE1_PIN(78, "WF0_HB0"),
555 + MT7986_TYPE1_PIN(79, "WF0_HB0_B"),
556 + MT7986_TYPE1_PIN(80, "WF0_HB5"),
557 + MT7986_TYPE1_PIN(81, "WF0_HB6"),
558 + MT7986_TYPE1_PIN(82, "WF0_HB7"),
559 + MT7986_TYPE1_PIN(83, "WF0_HB8"),
560 + MT7986_TYPE1_PIN(84, "WF0_HB9"),
561 + MT7986_TYPE1_PIN(85, "WF0_HB10"),
562 + MT7986_TYPE1_PIN(86, "WF1_DIG_RESETB"),
563 + MT7986_TYPE1_PIN(87, "WF1_CBA_RESETB"),
564 + MT7986_TYPE1_PIN(88, "WF1_XO_REQ"),
565 + MT7986_TYPE1_PIN(89, "WF1_TOP_CLK"),
566 + MT7986_TYPE1_PIN(90, "WF1_TOP_DATA"),
567 + MT7986_TYPE1_PIN(91, "WF1_HB1"),
568 + MT7986_TYPE1_PIN(92, "WF1_HB2"),
569 + MT7986_TYPE1_PIN(93, "WF1_HB3"),
570 + MT7986_TYPE1_PIN(94, "WF1_HB4"),
571 + MT7986_TYPE1_PIN(95, "WF1_HB0"),
572 + MT7986_TYPE1_PIN(96, "WF1_HB0_B"),
573 + MT7986_TYPE1_PIN(97, "WF1_HB5"),
574 + MT7986_TYPE1_PIN(98, "WF1_HB6"),
575 + MT7986_TYPE1_PIN(99, "WF1_HB7"),
576 + MT7986_TYPE1_PIN(100, "WF1_HB8"),
579 +static const struct mtk_io_type_desc mt7986_io_type_desc[] = {
582 + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
583 + .drive_set = mtk_pinconf_drive_set_v1,
584 + .input_enable = mtk_pinconf_input_enable_v1,
588 + .bias_set = mtk_pinconf_bias_set_pu_pd,
589 + .drive_set = mtk_pinconf_drive_set_v1,
590 + .input_enable = mtk_pinconf_input_enable_v1,
594 +/* List all groups consisting of these pins dedicated to the enablement of
595 + * certain hardware block and the corresponding mode for all of the pins.
596 + * The hardware probably has multiple combinations of these pinouts.
599 +static int mt7986_watchdog_pins[] = { 0, };
600 +static int mt7986_watchdog_funcs[] = { 1, };
602 +static int mt7986_wifi_led_pins[] = { 1, 2, };
603 +static int mt7986_wifi_led_funcs[] = { 1, 1, };
605 +static int mt7986_i2c_pins[] = { 3, 4, };
606 +static int mt7986_i2c_funcs[] = { 1, 1, };
608 +static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
609 +static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
611 +static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
612 +static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
614 +static int mt7986_pwm1_1_pins[] = { 20, };
615 +static int mt7986_pwm1_1_funcs[] = { 2, };
617 +static int mt7986_pwm0_pins[] = { 21, };
618 +static int mt7986_pwm0_funcs[] = { 1, };
620 +static int mt7986_pwm1_0_pins[] = { 22, };
621 +static int mt7986_pwm1_0_funcs[] = { 1, };
623 +static int mt7986_emmc_45_pins[] = {
624 + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
625 +static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
627 +static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
628 +static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
630 +static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
631 +static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
633 +static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
634 +static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
636 +static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
637 +static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
639 +static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
640 +static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
642 +static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
643 +static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
645 +static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
646 +static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
648 +static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
649 +static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
651 +static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
652 +static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
654 +static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
655 +static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
657 +static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
658 +static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
660 +static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
661 +static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
663 +static int mt7986_uart0_pins[] = { 39, 40, };
664 +static int mt7986_uart0_funcs[] = { 1, 1, };
666 +static int mt7986_pcie_reset_pins[] = { 41, };
667 +static int mt7986_pcie_reset_funcs[] = { 1, };
669 +static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
670 +static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
672 +static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
673 +static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
675 +static int mt7986_emmc_51_pins[] = {
676 + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
677 +static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
679 +static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
680 +static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
682 +static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
683 +static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
685 +static int mt7986_switch_int_pins[] = { 66, };
686 +static int mt7986_switch_int_funcs[] = { 1, };
688 +static int mt7986_mdc_mdio_pins[] = { 67, 68, };
689 +static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
691 +static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
692 +static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
694 +static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
695 +static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
697 +static int mt7986_wf_dbdc_pins[] = {
698 + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
699 +static int mt7986_wf_dbdc_funcs[] = {
700 + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
702 +static int mt7986_pcie_clk_pins[] = { 9, };
703 +static int mt7986_pcie_clk_funcs[] = { 1, };
705 +static int mt7986_pcie_wake_pins[] = { 10, };
706 +static int mt7986_pcie_wake_funcs[] = { 1, };
708 +static const struct mtk_group_desc mt7986_groups[] = {
709 + PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
710 + PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
711 + PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
712 + PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
713 + PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
714 + PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
715 + PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
716 + PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
717 + PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
718 + PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
719 + PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
720 + PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
721 + PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
722 + PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
723 + PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
724 + PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
725 + PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
726 + PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
727 + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
728 + PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
729 + PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
730 + PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
731 + PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
732 + PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
733 + PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
734 + PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
735 + PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
736 + PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
737 + PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
738 + PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
739 + PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
740 + PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
741 + PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
742 + PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
743 + PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
746 +/* Joint those groups owning the same capability in user point of view which
747 + * allows that people tend to use through the device tree.
750 +static const char *const mt7986_audio_groups[] = { "pcm", "i2s" };
751 +static const char *const mt7986_emmc_groups[] = { "emmc_45", "emmc_51", };
752 +static const char *const mt7986_ethernet_groups[] = { "switch_int",
754 +static const char *const mt7986_i2c_groups[] = { "i2c", };
755 +static const char *const mt7986_led_groups[] = { "wifi_led", };
756 +static const char *const mt7986_flash_groups[] = { "snfi", };
757 +static const char *const mt7986_pcie_groups[] = { "pcie_clk", "pcie_wake",
759 +static const char *const mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
760 +static const char *const mt7986_spi_groups[] = { "spi0", "spi0_wp_hold",
761 + "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
762 +static const char *const mt7986_uart_groups[] = { "uart1_0", "uart1_1",
763 + "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0", "uart2_1",
764 + "uart0", "uart1", "uart2", };
765 +static const char *const mt7986_wdt_groups[] = { "watchdog", };
766 +static const char *const mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
768 +static const struct mtk_function_desc mt7986_functions[] = {
769 + {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
770 + {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
771 + {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
772 + {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
773 + {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
774 + {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
775 + {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
776 + {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
777 + {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
778 + {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
779 + {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
780 + {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
783 +static struct mtk_pinctrl_soc mt7986_data = {
784 + .name = "mt7986_pinctrl",
785 + .reg_cal = mt7986_reg_cals,
786 + .pins = mt7986_pins,
787 + .npins = ARRAY_SIZE(mt7986_pins),
788 + .grps = mt7986_groups,
789 + .ngrps = ARRAY_SIZE(mt7986_groups),
790 + .funcs = mt7986_functions,
791 + .nfuncs = ARRAY_SIZE(mt7986_functions),
792 + .io_type = mt7986_io_type_desc,
793 + .ntype = ARRAY_SIZE(mt7986_io_type_desc),
795 + .base_names = mt7986_pinctrl_register_base_names,
796 + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
800 +static int mtk_pinctrl_mt7986_probe(struct udevice *dev)
802 + return mtk_pinctrl_common_probe(dev, &mt7986_data);
805 +static const struct udevice_id mt7986_pctrl_match[] = {
806 + {.compatible = "mediatek,mt7986-pinctrl"},
810 +U_BOOT_DRIVER(mt7986_pinctrl) = {
811 + .name = "mt7986_pinctrl",
812 + .id = UCLASS_PINCTRL,
813 + .of_match = mt7986_pctrl_match,
814 + .ops = &mtk_pinctrl_ops,
815 + .probe = mtk_pinctrl_mt7986_probe,
816 + .priv_auto = sizeof(struct mtk_pinctrl_priv),
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