git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   2 Subject: [PATCH 2/2] net: phy: pick Broadcom drivers updates from net-next for
   3  4.11
   4 MIME-Version: 1.0
   5 Content-Type: text/plain; charset=UTF-8
   6 Content-Transfer-Encoding: 8bit
   7
   8 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
   9 ---
  10
  11 --- a/drivers/net/phy/bcm7xxx.c
  12 +++ b/drivers/net/phy/bcm7xxx.c
  13 @@ -163,12 +163,43 @@ static int bcm7xxx_28nm_e0_plus_afe_conf
  14         return 0;
  15  }
  16
  17 +static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
  18 +{
  19 +       /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
  20 +       bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
  21 +
  22 +       /* Cut master bias current by 2% to compensate for RC_CAL offset */
  23 +       bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
  24 +
  25 +       /* Improve hybrid leakage */
  26 +       bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
  27 +
  28 +       /* Change rx_on_tune 8 to 0xf */
  29 +       bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
  30 +
  31 +       /* Change 100Tx EEE bandwidth */
  32 +       bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
  33 +
  34 +       /* Enable ffe zero detection for Vitesse interoperability */
  35 +       bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
  36 +
  37 +       r_rc_cal_reset(phydev);
  38 +
  39 +       return 0;
  40 +}
  41 +
  42  static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
  43  {
  44         u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
  45         u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
  46         int ret = 0;
  47
  48 +       /* Newer devices have moved the revision information back into a
  49 +        * standard location in MII_PHYS_ID[23]
  50 +        */
  51 +       if (rev == 0)
  52 +               rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
  53 +
  54         pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
  55                      dev_name(&phydev->dev), phydev->drv->name, rev, patch);
  56
  57 @@ -192,6 +223,9 @@ static int bcm7xxx_28nm_config_init(stru
  58         case 0x10:
  59                 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
  60                 break;
  61 +       case 0x01:
  62 +               ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
  63 +               break;
  64         default:
  65                 break;
  66         }
  67 @@ -336,6 +370,7 @@ static int bcm7xxx_suspend(struct phy_de
  68
  69  static struct phy_driver bcm7xxx_driver[] = {
  70         BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
  71 +       BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
  72         BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
  73         BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
  74         BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
  75 @@ -350,6 +385,7 @@ static struct phy_driver bcm7xxx_driver[
  76
  77  static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
  78         { PHY_ID_BCM7250, 0xfffffff0, },
  79 +       { PHY_ID_BCM7278, 0xfffffff0, },
  80         { PHY_ID_BCM7364, 0xfffffff0, },
  81         { PHY_ID_BCM7366, 0xfffffff0, },
  82         { PHY_ID_BCM7346, 0xfffffff0, },
  83 --- a/drivers/net/phy/broadcom.c
  84 +++ b/drivers/net/phy/broadcom.c
  85 @@ -395,12 +395,10 @@ static int bcm54612e_config_aneg(struct
  86             (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
  87                 u16 reg;
  88
  89 -               /* Errata: reads require filling in the write selector field */
  90 -               bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  91 -                                    MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
  92 -               reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
  93 +               reg = bcm54xx_auxctl_read(phydev,
  94 +                                         MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
  95                 /* Disable RXD to RXC delay (default set) */
  96 -               reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
  97 +               reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  98                 /* Clear shadow selector field */
  99                 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
 100                 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
 101 --- a/include/linux/brcmphy.h
 102 +++ b/include/linux/brcmphy.h
 103 @@ -24,6 +24,7 @@
 104  #define PHY_ID_BCM57780                        0x03625d90
 105
 106  #define PHY_ID_BCM7250                 0xae025280
 107 +#define PHY_ID_BCM7278                 0xae0251a0
 108  #define PHY_ID_BCM7364                 0xae025260
 109  #define PHY_ID_BCM7366                 0x600d8490
 110  #define PHY_ID_BCM7346                 0x600d8650
 111 @@ -103,18 +104,17 @@
 112  /*
 113   * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
 114   */
 115 -#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL      0x0000
 116 +#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL      0x00
 117  #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB         0x0400
 118  #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA      0x0800
 119
 120 -#define MII_BCM54XX_AUXCTL_MISC_WREN   0x8000
 121 -#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW   0x0100
 122 -#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX    0x0200
 123 -#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC     0x7000
 124 -#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC        0x0007
 125 -#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT  12
 126 -#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN  (1 << 8)
 127 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC                        0x07
 128 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN   0x0010
 129 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN  0x0100
 130 +#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX            0x0200
 131 +#define MII_BCM54XX_AUXCTL_MISC_WREN                   0x8000
 132
 133 +#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT  12
 134  #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK        0x0007
 135
 136  /*