d1544b1d3609cbf1fd42c1e0a85f707d30d54e01
[openwrt/staging/neocturne.git] /
1 From b0fcb4b413028376894feaaaf62bcb09ab1b52f2 Mon Sep 17 00:00:00 2001
2 From: Mathias Kresin <dev@kresin.me>
3 Date: Thu, 13 Apr 2017 09:23:54 +0200
4 Subject: [PATCH] mtd: spi-nor: enable stateless 4b op codes for mx25u25635f
5
6 All required stateless 4-byte op codes are supported by this flash
7 chip. The stateless 4-byte support can't be autodetected due to a
8 missing 4-byte Address Instruction Table in SFDP.
9
10 Fixes hangs on reboot for SoCs expecting the flash chip in 3byte mode.
11
12 Signed-off-by: Mathias Kresin <dev@kresin.me>
13 Acked-by: Marek Vasut <marek.vasut@gmail.com>
14 Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
15 ---
16 drivers/mtd/spi-nor/spi-nor.c | 2 +-
17 1 file changed, 1 insertion(+), 1 deletion(-)
18
19 --- a/drivers/mtd/spi-nor/spi-nor.c
20 +++ b/drivers/mtd/spi-nor/spi-nor.c
21 @@ -1023,7 +1023,7 @@ static const struct flash_info spi_nor_i
22 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
23 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
24 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
25 - { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
26 + { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
27 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
28 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
29 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },