git.openwrt.org Git - openwrt/staging/hauke.git/blob

   1 From 1640daf71d5230997e9b75a550d3800bede298db Mon Sep 17 00:00:00 2001
   2 From: Shengjiu Wang <shengjiu.wang@freescale.com>
   3 Date: Wed, 12 Jul 2017 18:19:25 +0800
   4 Subject: [PATCH] MLK-15960-1: ASoC: fsl_sai: update fifo_depth for different
   5  platform
   6
   7 The fifo_depth is changed to 64 in imx8qm/imx8qxp, in imx8mq, the
   8 fifo_depth is 128. which is mentioned in their ADD.
   9
  10 Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
  11 ---
  12  sound/soc/fsl/fsl_sai.c | 14 ++++++++------
  13  1 file changed, 8 insertions(+), 6 deletions(-)
  14
  15 --- a/sound/soc/fsl/fsl_sai.c
  16 +++ b/sound/soc/fsl/fsl_sai.c
  17 @@ -72,7 +72,7 @@ static struct fsl_sai_soc_data fsl_sai_i
  18         .imx = true,
  19         .dataline = 0xff,
  20         .fifos = 8,
  21 -       .fifo_depth = 32,
  22 +       .fifo_depth = 128,
  23         .flags = 0,
  24         .reg_offset = 8,
  25         .constrain_period_size = false,
  26 @@ -82,7 +82,7 @@ static struct fsl_sai_soc_data fsl_sai_i
  27         .imx = true,
  28         .dataline = 0x3,
  29         .fifos = 1,
  30 -       .fifo_depth = 32,
  31 +       .fifo_depth = 64,
  32         .flags = 0,
  33         .reg_offset = 0,
  34         .constrain_period_size = true,
  35 @@ -759,10 +759,12 @@ static int fsl_sai_dai_probe(struct snd_
  36         regmap_write(sai->regmap, FSL_SAI_TCSR(offset), 0);
  37         regmap_write(sai->regmap, FSL_SAI_RCSR(offset), 0);
  38
  39 -       regmap_update_bits(sai->regmap, FSL_SAI_TCR1(offset), FSL_SAI_CR1_RFW_MASK,
  40 -                          sai->soc->fifo_depth - FSL_SAI_MAXBURST_TX);
  41 -       regmap_update_bits(sai->regmap, FSL_SAI_RCR1(offset), FSL_SAI_CR1_RFW_MASK,
  42 -                          FSL_SAI_MAXBURST_RX - 1);
  43 +       regmap_update_bits(sai->regmap, FSL_SAI_TCR1(offset),
  44 +                               sai->soc->fifo_depth - 1,
  45 +                               sai->soc->fifo_depth - FSL_SAI_MAXBURST_TX);
  46 +       regmap_update_bits(sai->regmap, FSL_SAI_RCR1(offset),
  47 +                               sai->soc->fifo_depth - 1,
  48 +                               FSL_SAI_MAXBURST_RX - 1);
  49
  50         snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
  51                                 &sai->dma_params_rx);