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1 From 00901251b7fc718fab5f47bda592996ba4556dd5 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Fri, 17 Feb 2023 15:34:30 +0100
4 Subject: [PATCH 0612/1085] drm/vc4: hdmi: Add support for BCM2712 HDMI
5 controllers
6
7 The HDMI controllers found in the BCM2712 are largely the ones found in
8 the BCM2711 with a different PHY.
9
10 There's some difference with how timings are split between registers,
11 and HDMI1 is now able to run at 4k/60Hz.
12
13 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
14 ---
15 drivers/gpu/drm/vc4/vc4_hdmi.c | 82 +++-
16 drivers/gpu/drm/vc4/vc4_hdmi.h | 4 +
17 drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 640 ++++++++++++++++++++++++++++
18 drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 217 ++++++++++
19 4 files changed, 937 insertions(+), 6 deletions(-)
20
21 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
22 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
23 @@ -1102,6 +1102,7 @@ static void vc4_hdmi_encoder_post_crtc_d
24 {
25 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
26 struct drm_device *drm = vc4_hdmi->connector.dev;
27 + struct vc4_dev *vc4 = to_vc4_dev(drm);
28 unsigned long flags;
29 int idx;
30
31 @@ -1118,14 +1119,25 @@ static void vc4_hdmi_encoder_post_crtc_d
32
33 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
34
35 + if (vc4->gen >= VC4_GEN_6)
36 + HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
37 + VC4_HD_VID_CTL_BLANKPIX);
38 +
39 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
40
41 mdelay(1);
42
43 - spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
44 - HDMI_WRITE(HDMI_VID_CTL,
45 - HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
46 - spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
47 + /*
48 + * TODO: This should work on BCM2712, but doesn't for some
49 + * reason and result in a system lockup.
50 + */
51 + if (vc4->gen < VC4_GEN_6) {
52 + spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
53 + HDMI_WRITE(HDMI_VID_CTL,
54 + HDMI_READ(HDMI_VID_CTL) &
55 + ~VC4_HD_VID_CTL_ENABLE);
56 + spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
57 + }
58
59 vc4_hdmi_disable_scrambling(encoder);
60
61 @@ -1753,7 +1765,6 @@ static void vc4_hdmi_encoder_pre_crtc_co
62 goto err_put_runtime_pm;
63 }
64
65 -
66 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
67
68 if (tmds_char_rate > 297000000)
69 @@ -1858,6 +1869,7 @@ static void vc4_hdmi_encoder_post_crtc_e
70 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
71
72 HDMI_WRITE(HDMI_VID_CTL,
73 + HDMI_READ(HDMI_VID_CTL) |
74 VC4_HD_VID_CTL_ENABLE |
75 VC4_HD_VID_CTL_CLRRGB |
76 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
77 @@ -3751,7 +3763,9 @@ static int vc4_hdmi_bind(struct device *
78 return ret;
79
80 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
81 - of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
82 + of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") ||
83 + of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") ||
84 + of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) &&
85 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
86 clk_prepare_enable(vc4_hdmi->pixel_clock);
87 clk_prepare_enable(vc4_hdmi->hsm_clock);
88 @@ -3885,10 +3899,66 @@ static const struct vc4_hdmi_variant bcm
89 .hp_detect = vc5_hdmi_hp_detect,
90 };
91
92 +static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
93 + .encoder_type = VC4_ENCODER_TYPE_HDMI0,
94 + .debugfs_name = "hdmi0_regs",
95 + .card_name = "vc4-hdmi-0",
96 + .max_pixel_clock = 600000000,
97 + .registers = vc6_hdmi_hdmi0_fields,
98 + .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields),
99 + .phy_lane_mapping = {
100 + PHY_LANE_0,
101 + PHY_LANE_1,
102 + PHY_LANE_2,
103 + PHY_LANE_CK,
104 + },
105 + .unsupported_odd_h_timings = true,
106 + .external_irq_controller = true,
107 +
108 + .init_resources = vc5_hdmi_init_resources,
109 + .csc_setup = vc5_hdmi_csc_setup,
110 + .reset = vc5_hdmi_reset,
111 + .set_timings = vc5_hdmi_set_timings,
112 + .phy_init = vc6_hdmi_phy_init,
113 + .phy_disable = vc6_hdmi_phy_disable,
114 + .channel_map = vc5_hdmi_channel_map,
115 + .supports_hdr = true,
116 + .hp_detect = vc5_hdmi_hp_detect,
117 +};
118 +
119 +static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
120 + .encoder_type = VC4_ENCODER_TYPE_HDMI1,
121 + .debugfs_name = "hdmi1_regs",
122 + .card_name = "vc4-hdmi-1",
123 + .max_pixel_clock = 600000000,
124 + .registers = vc6_hdmi_hdmi1_fields,
125 + .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields),
126 + .phy_lane_mapping = {
127 + PHY_LANE_0,
128 + PHY_LANE_1,
129 + PHY_LANE_2,
130 + PHY_LANE_CK,
131 + },
132 + .unsupported_odd_h_timings = true,
133 + .external_irq_controller = true,
134 +
135 + .init_resources = vc5_hdmi_init_resources,
136 + .csc_setup = vc5_hdmi_csc_setup,
137 + .reset = vc5_hdmi_reset,
138 + .set_timings = vc5_hdmi_set_timings,
139 + .phy_init = vc6_hdmi_phy_init,
140 + .phy_disable = vc6_hdmi_phy_disable,
141 + .channel_map = vc5_hdmi_channel_map,
142 + .supports_hdr = true,
143 + .hp_detect = vc5_hdmi_hp_detect,
144 +};
145 +
146 static const struct of_device_id vc4_hdmi_dt_match[] = {
147 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
148 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
149 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
150 + { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant },
151 + { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant },
152 {}
153 };
154
155 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
156 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
157 @@ -263,4 +263,8 @@ void vc5_hdmi_phy_disable(struct vc4_hdm
158 void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
159 void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
160
161 +void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
162 + struct vc4_hdmi_connector_state *vc4_conn_state);
163 +void vc6_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
164 +
165 #endif /* _VC4_HDMI_H_ */
166 --- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
167 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
168 @@ -125,6 +125,48 @@
169 #define VC4_HDMI_RM_FORMAT_SHIFT_SHIFT 24
170 #define VC4_HDMI_RM_FORMAT_SHIFT_MASK VC4_MASK(25, 24)
171
172 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BG_PWRUP BIT(8)
173 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_LDO_PWRUP BIT(7)
174 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BIAS_PWRUP BIT(6)
175 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_RNDGEN_PWRUP BIT(4)
176 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_CK_PWRUP BIT(3)
177 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_2_PWRUP BIT(2)
178 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_1_PWRUP BIT(1)
179 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_0_PWRUP BIT(0)
180 +
181 +#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS BIT(13)
182 +#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK VC4_MASK(9, 0)
183 +
184 +#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL_MASK VC4_MASK(3, 2)
185 +#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK VC4_MASK(1, 0)
186 +
187 +#define VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_EN BIT(10)
188 +#define VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_MASK VC4_MASK(9, 0)
189 +
190 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL_MASK VC4_MASK(31, 28)
191 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE_MASK VC4_MASK(27, 27)
192 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL_MASK VC4_MASK(26, 26)
193 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN_MASK VC4_MASK(25, 25)
194 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL_MASK VC4_MASK(24, 23)
195 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN_MASK VC4_MASK(22, 22)
196 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL_MASK VC4_MASK(21, 21)
197 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN_MASK VC4_MASK(20, 20)
198 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL_MASK VC4_MASK(19, 18)
199 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN_MASK VC4_MASK(17, 17)
200 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN_MASK VC4_MASK(16, 16)
201 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL_MASK VC4_MASK(15, 12)
202 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN_MASK VC4_MASK(11, 11)
203 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT_MASK VC4_MASK(10, 8)
204 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT_MASK VC4_MASK(7, 5)
205 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING_MASK VC4_MASK(4, 3)
206 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING_MASK VC4_MASK(2, 1)
207 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN_MASK VC4_MASK(0, 0)
208 +
209 +#define VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_PLLPOST_RESETB BIT(1)
210 +#define VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_RESETB BIT(0)
211 +
212 +#define VC6_HDMI_TX_PHY_PLL_POWERUP_CTL_PLL_PWRUP BIT(0)
213 +
214 #define OSCILLATOR_FREQUENCY 54000000
215
216 void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
217 @@ -558,3 +600,601 @@ void vc5_hdmi_phy_rng_disable(struct vc4
218 VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN);
219 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
220 }
221 +
222 +#define VC6_VCO_MIN_FREQ (8ULL * 1000 * 1000 * 1000)
223 +#define VC6_VCO_MAX_FREQ (12ULL * 1000 * 1000 * 1000)
224 +
225 +static unsigned long long
226 +vc6_phy_get_vco_freq(unsigned long long tmds_rate, unsigned int *vco_div)
227 +{
228 + unsigned int min_div;
229 + unsigned int max_div;
230 + unsigned int div;
231 +
232 + div = 0;
233 + while (tmds_rate * div * 10 < VC6_VCO_MIN_FREQ)
234 + div++;
235 + min_div = div;
236 +
237 + while (tmds_rate * (div + 1) * 10 < VC6_VCO_MAX_FREQ)
238 + div++;
239 + max_div = div;
240 +
241 + div = min_div + (max_div - min_div) / 2;
242 +
243 + *vco_div = div;
244 + return tmds_rate * div * 10;
245 +}
246 +
247 +struct vc6_phy_lane_settings {
248 + unsigned int ext_current_ctl:4;
249 + unsigned int ffe_enable:1;
250 + unsigned int slew_rate_ctl:1;
251 + unsigned int ffe_post_tap_en:1;
252 + unsigned int ldmos_bias_ctl:2;
253 + unsigned int com_mode_ldmos_en:1;
254 + unsigned int edge_sel:1;
255 + unsigned int ext_current_src_hs_en:1;
256 + unsigned int term_ctl:2;
257 + unsigned int ext_current_src_en:1;
258 + unsigned int int_current_src_en:1;
259 + unsigned int int_current_ctl:4;
260 + unsigned int int_current_src_hs_en:1;
261 + unsigned int main_tap_current_select:3;
262 + unsigned int post_tap_current_select:3;
263 + unsigned int slew_ctl_slow_loading:2;
264 + unsigned int slew_ctl_slow_driving:2;
265 + unsigned int ffe_pre_tap_en:1;
266 +};
267 +
268 +struct vc6_phy_settings {
269 + unsigned long long min_rate;
270 + unsigned long long max_rate;
271 + struct vc6_phy_lane_settings channel[3];
272 + struct vc6_phy_lane_settings clock;
273 +};
274 +
275 +static const struct vc6_phy_settings vc6_hdmi_phy_settings[] = {
276 + {
277 + 0, 222000000,
278 + {
279 + {
280 + /* 200mA */
281 + .ext_current_ctl = 8,
282 +
283 + /* 0.85V */
284 + .ldmos_bias_ctl = 1,
285 +
286 + /* Enable External Current Source */
287 + .ext_current_src_en = 1,
288 +
289 + /* 200mA */
290 + .int_current_ctl = 8,
291 +
292 + /* 17.6 mA */
293 + .main_tap_current_select = 7,
294 + },
295 + {
296 + /* 200mA */
297 + .ext_current_ctl = 8,
298 +
299 + /* 0.85V */
300 + .ldmos_bias_ctl = 1,
301 +
302 + /* Enable External Current Source */
303 + .ext_current_src_en = 1,
304 +
305 + /* 200mA */
306 + .int_current_ctl = 8,
307 +
308 + /* 17.6 mA */
309 + .main_tap_current_select = 7,
310 + },
311 + {
312 + /* 200mA */
313 + .ext_current_ctl = 8,
314 +
315 + /* 0.85V */
316 + .ldmos_bias_ctl = 1,
317 +
318 + /* Enable External Current Source */
319 + .ext_current_src_en = 1,
320 +
321 + /* 200mA */
322 + .int_current_ctl = 8,
323 +
324 + /* 17.6 mA */
325 + .main_tap_current_select = 7,
326 + },
327 + },
328 + {
329 + /* 200mA */
330 + .ext_current_ctl = 8,
331 +
332 + /* 0.85V */
333 + .ldmos_bias_ctl = 1,
334 +
335 + /* Enable External Current Source */
336 + .ext_current_src_en = 1,
337 +
338 + /* 200mA */
339 + .int_current_ctl = 8,
340 +
341 + /* 17.6 mA */
342 + .main_tap_current_select = 7,
343 + },
344 + },
345 + {
346 + 222000001, 297000000,
347 + {
348 + {
349 + /* 200mA and 180mA ?! */
350 + .ext_current_ctl = 12,
351 +
352 + /* 0.85V */
353 + .ldmos_bias_ctl = 1,
354 +
355 + /* 100 Ohm */
356 + .term_ctl = 1,
357 +
358 + /* Enable External Current Source */
359 + .ext_current_src_en = 1,
360 +
361 + /* Enable Internal Current Source */
362 + .int_current_src_en = 1,
363 + },
364 + {
365 + /* 200mA and 180mA ?! */
366 + .ext_current_ctl = 12,
367 +
368 + /* 0.85V */
369 + .ldmos_bias_ctl = 1,
370 +
371 + /* 100 Ohm */
372 + .term_ctl = 1,
373 +
374 + /* Enable External Current Source */
375 + .ext_current_src_en = 1,
376 +
377 + /* Enable Internal Current Source */
378 + .int_current_src_en = 1,
379 + },
380 + {
381 + /* 200mA and 180mA ?! */
382 + .ext_current_ctl = 12,
383 +
384 + /* 0.85V */
385 + .ldmos_bias_ctl = 1,
386 +
387 + /* 100 Ohm */
388 + .term_ctl = 1,
389 +
390 + /* Enable External Current Source */
391 + .ext_current_src_en = 1,
392 +
393 + /* Enable Internal Current Source */
394 + .int_current_src_en = 1,
395 + },
396 + },
397 + {
398 + /* 200mA and 180mA ?! */
399 + .ext_current_ctl = 12,
400 +
401 + /* 0.85V */
402 + .ldmos_bias_ctl = 1,
403 +
404 + /* 100 Ohm */
405 + .term_ctl = 1,
406 +
407 + /* Enable External Current Source */
408 + .ext_current_src_en = 1,
409 +
410 + /* Enable Internal Current Source */
411 + .int_current_src_en = 1,
412 +
413 + /* Internal Current Source Half Swing Enable*/
414 + .int_current_src_hs_en = 1,
415 + },
416 + },
417 + {
418 + 297000001, 597000044,
419 + {
420 + {
421 + /* 200mA */
422 + .ext_current_ctl = 8,
423 +
424 + /* Normal Slew Rate Control */
425 + .slew_rate_ctl = 1,
426 +
427 + /* 0.85V */
428 + .ldmos_bias_ctl = 1,
429 +
430 + /* 50 Ohms */
431 + .term_ctl = 3,
432 +
433 + /* Enable External Current Source */
434 + .ext_current_src_en = 1,
435 +
436 + /* Enable Internal Current Source */
437 + .int_current_src_en = 1,
438 +
439 + /* 200mA */
440 + .int_current_ctl = 8,
441 +
442 + /* 17.6 mA */
443 + .main_tap_current_select = 7,
444 + },
445 + {
446 + /* 200mA */
447 + .ext_current_ctl = 8,
448 +
449 + /* Normal Slew Rate Control */
450 + .slew_rate_ctl = 1,
451 +
452 + /* 0.85V */
453 + .ldmos_bias_ctl = 1,
454 +
455 + /* 50 Ohms */
456 + .term_ctl = 3,
457 +
458 + /* Enable External Current Source */
459 + .ext_current_src_en = 1,
460 +
461 + /* Enable Internal Current Source */
462 + .int_current_src_en = 1,
463 +
464 + /* 200mA */
465 + .int_current_ctl = 8,
466 +
467 + /* 17.6 mA */
468 + .main_tap_current_select = 7,
469 + },
470 + {
471 + /* 200mA */
472 + .ext_current_ctl = 8,
473 +
474 + /* Normal Slew Rate Control */
475 + .slew_rate_ctl = 1,
476 +
477 + /* 0.85V */
478 + .ldmos_bias_ctl = 1,
479 +
480 + /* 50 Ohms */
481 + .term_ctl = 3,
482 +
483 + /* Enable External Current Source */
484 + .ext_current_src_en = 1,
485 +
486 + /* Enable Internal Current Source */
487 + .int_current_src_en = 1,
488 +
489 + /* 200mA */
490 + .int_current_ctl = 8,
491 +
492 + /* 17.6 mA */
493 + .main_tap_current_select = 7,
494 + },
495 + },
496 + {
497 + /* 200mA */
498 + .ext_current_ctl = 8,
499 +
500 + /* Normal Slew Rate Control */
501 + .slew_rate_ctl = 1,
502 +
503 + /* 0.85V */
504 + .ldmos_bias_ctl = 1,
505 +
506 + /* External Current Source Half Swing Enable*/
507 + .ext_current_src_hs_en = 1,
508 +
509 + /* 50 Ohms */
510 + .term_ctl = 3,
511 +
512 + /* Enable External Current Source */
513 + .ext_current_src_en = 1,
514 +
515 + /* Enable Internal Current Source */
516 + .int_current_src_en = 1,
517 +
518 + /* 200mA */
519 + .int_current_ctl = 8,
520 +
521 + /* Internal Current Source Half Swing Enable*/
522 + .int_current_src_hs_en = 1,
523 +
524 + /* 17.6 mA */
525 + .main_tap_current_select = 7,
526 + },
527 + },
528 +};
529 +
530 +static const struct vc6_phy_settings *
531 +vc6_phy_get_settings(unsigned long long tmds_rate)
532 +{
533 + unsigned int count = ARRAY_SIZE(vc6_hdmi_phy_settings);
534 + unsigned int i;
535 +
536 + for (i = 0; i < count; i++) {
537 + const struct vc6_phy_settings *s = &vc6_hdmi_phy_settings[i];
538 +
539 + if (tmds_rate >= s->min_rate && tmds_rate <= s->max_rate)
540 + return s;
541 + }
542 +
543 + /*
544 + * If the pixel clock exceeds our max setting, try the max
545 + * setting anyway.
546 + */
547 + return &vc6_hdmi_phy_settings[count - 1];
548 +}
549 +
550 +static const struct vc6_phy_lane_settings *
551 +vc6_phy_get_channel_settings(enum vc4_hdmi_phy_channel chan,
552 + unsigned long long tmds_rate)
553 +{
554 + const struct vc6_phy_settings *settings = vc6_phy_get_settings(tmds_rate);
555 +
556 + if (chan == PHY_LANE_CK)
557 + return &settings->clock;
558 +
559 + return &settings->channel[chan];
560 +}
561 +
562 +static void vc6_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi)
563 +{
564 + lockdep_assert_held(&vc4_hdmi->hw_lock);
565 +
566 + HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
567 + HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL, 0);
568 +}
569 +
570 +void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
571 + struct vc4_hdmi_connector_state *conn_state)
572 +{
573 + const struct vc6_phy_lane_settings *chan0_settings;
574 + const struct vc6_phy_lane_settings *chan1_settings;
575 + const struct vc6_phy_lane_settings *chan2_settings;
576 + const struct vc6_phy_lane_settings *clock_settings;
577 + const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
578 + unsigned long long pixel_freq = conn_state->tmds_char_rate;
579 + unsigned long long vco_freq;
580 + unsigned char word_sel;
581 + unsigned long flags;
582 + unsigned int vco_div;
583 +
584 + vco_freq = vc6_phy_get_vco_freq(pixel_freq, &vco_div);
585 +
586 + spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
587 +
588 + vc6_hdmi_reset_phy(vc4_hdmi);
589 +
590 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_0, 0x810c6000);
591 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_1, 0x00b8c451);
592 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_2, 0x46402e31);
593 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_3, 0x00b8c005);
594 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_4, 0x42410261);
595 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_5, 0xcc021001);
596 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_6, 0xc8301c80);
597 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_7, 0xb0804444);
598 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_8, 0xf80f8000);
599 +
600 + HDMI_WRITE(HDMI_TX_PHY_PLL_REFCLK,
601 + VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS |
602 + VC4_SET_FIELD(54, VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ));
603 +
604 + HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0x7f);
605 +
606 + HDMI_WRITE(HDMI_RM_OFFSET,
607 + VC4_HDMI_RM_OFFSET_ONLY |
608 + VC4_SET_FIELD(phy_get_rm_offset(vco_freq),
609 + VC4_HDMI_RM_OFFSET_OFFSET));
610 +
611 + HDMI_WRITE(HDMI_TX_PHY_PLL_VCOCLK_DIV,
612 + VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_EN |
613 + VC4_SET_FIELD(vco_div,
614 + VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV));
615 +
616 + HDMI_WRITE(HDMI_TX_PHY_PLL_CFG,
617 + VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CFG_PDIV));
618 +
619 + HDMI_WRITE(HDMI_TX_PHY_PLL_POST_KDIV,
620 + VC4_SET_FIELD(2, VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL) |
621 + VC4_SET_FIELD(1, VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV));
622 +
623 + chan0_settings =
624 + vc6_phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_0],
625 + pixel_freq);
626 + HDMI_WRITE(HDMI_TX_PHY_CTL_0,
627 + VC4_SET_FIELD(chan0_settings->ext_current_ctl,
628 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL) |
629 + VC4_SET_FIELD(chan0_settings->ffe_enable,
630 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE) |
631 + VC4_SET_FIELD(chan0_settings->slew_rate_ctl,
632 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL) |
633 + VC4_SET_FIELD(chan0_settings->ffe_post_tap_en,
634 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN) |
635 + VC4_SET_FIELD(chan0_settings->ldmos_bias_ctl,
636 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL) |
637 + VC4_SET_FIELD(chan0_settings->com_mode_ldmos_en,
638 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN) |
639 + VC4_SET_FIELD(chan0_settings->edge_sel,
640 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL) |
641 + VC4_SET_FIELD(chan0_settings->ext_current_src_hs_en,
642 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN) |
643 + VC4_SET_FIELD(chan0_settings->term_ctl,
644 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL) |
645 + VC4_SET_FIELD(chan0_settings->ext_current_src_en,
646 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN) |
647 + VC4_SET_FIELD(chan0_settings->int_current_src_en,
648 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN) |
649 + VC4_SET_FIELD(chan0_settings->int_current_ctl,
650 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL) |
651 + VC4_SET_FIELD(chan0_settings->int_current_src_hs_en,
652 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN) |
653 + VC4_SET_FIELD(chan0_settings->main_tap_current_select,
654 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT) |
655 + VC4_SET_FIELD(chan0_settings->post_tap_current_select,
656 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT) |
657 + VC4_SET_FIELD(chan0_settings->slew_ctl_slow_loading,
658 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING) |
659 + VC4_SET_FIELD(chan0_settings->slew_ctl_slow_driving,
660 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING) |
661 + VC4_SET_FIELD(chan0_settings->ffe_pre_tap_en,
662 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN));
663 +
664 + chan1_settings =
665 + vc6_phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_1],
666 + pixel_freq);
667 + HDMI_WRITE(HDMI_TX_PHY_CTL_1,
668 + VC4_SET_FIELD(chan1_settings->ext_current_ctl,
669 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL) |
670 + VC4_SET_FIELD(chan1_settings->ffe_enable,
671 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE) |
672 + VC4_SET_FIELD(chan1_settings->slew_rate_ctl,
673 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL) |
674 + VC4_SET_FIELD(chan1_settings->ffe_post_tap_en,
675 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN) |
676 + VC4_SET_FIELD(chan1_settings->ldmos_bias_ctl,
677 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL) |
678 + VC4_SET_FIELD(chan1_settings->com_mode_ldmos_en,
679 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN) |
680 + VC4_SET_FIELD(chan1_settings->edge_sel,
681 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL) |
682 + VC4_SET_FIELD(chan1_settings->ext_current_src_hs_en,
683 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN) |
684 + VC4_SET_FIELD(chan1_settings->term_ctl,
685 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL) |
686 + VC4_SET_FIELD(chan1_settings->ext_current_src_en,
687 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN) |
688 + VC4_SET_FIELD(chan1_settings->int_current_src_en,
689 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN) |
690 + VC4_SET_FIELD(chan1_settings->int_current_ctl,
691 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL) |
692 + VC4_SET_FIELD(chan1_settings->int_current_src_hs_en,
693 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN) |
694 + VC4_SET_FIELD(chan1_settings->main_tap_current_select,
695 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT) |
696 + VC4_SET_FIELD(chan1_settings->post_tap_current_select,
697 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT) |
698 + VC4_SET_FIELD(chan1_settings->slew_ctl_slow_loading,
699 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING) |
700 + VC4_SET_FIELD(chan1_settings->slew_ctl_slow_driving,
701 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING) |
702 + VC4_SET_FIELD(chan1_settings->ffe_pre_tap_en,
703 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN));
704 +
705 + chan2_settings =
706 + vc6_phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_2],
707 + pixel_freq);
708 + HDMI_WRITE(HDMI_TX_PHY_CTL_2,
709 + VC4_SET_FIELD(chan2_settings->ext_current_ctl,
710 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL) |
711 + VC4_SET_FIELD(chan2_settings->ffe_enable,
712 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE) |
713 + VC4_SET_FIELD(chan2_settings->slew_rate_ctl,
714 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL) |
715 + VC4_SET_FIELD(chan2_settings->ffe_post_tap_en,
716 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN) |
717 + VC4_SET_FIELD(chan2_settings->ldmos_bias_ctl,
718 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL) |
719 + VC4_SET_FIELD(chan2_settings->com_mode_ldmos_en,
720 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN) |
721 + VC4_SET_FIELD(chan2_settings->edge_sel,
722 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL) |
723 + VC4_SET_FIELD(chan2_settings->ext_current_src_hs_en,
724 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN) |
725 + VC4_SET_FIELD(chan2_settings->term_ctl,
726 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL) |
727 + VC4_SET_FIELD(chan2_settings->ext_current_src_en,
728 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN) |
729 + VC4_SET_FIELD(chan2_settings->int_current_src_en,
730 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN) |
731 + VC4_SET_FIELD(chan2_settings->int_current_ctl,
732 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL) |
733 + VC4_SET_FIELD(chan2_settings->int_current_src_hs_en,
734 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN) |
735 + VC4_SET_FIELD(chan2_settings->main_tap_current_select,
736 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT) |
737 + VC4_SET_FIELD(chan2_settings->post_tap_current_select,
738 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT) |
739 + VC4_SET_FIELD(chan2_settings->slew_ctl_slow_loading,
740 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING) |
741 + VC4_SET_FIELD(chan2_settings->slew_ctl_slow_driving,
742 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING) |
743 + VC4_SET_FIELD(chan2_settings->ffe_pre_tap_en,
744 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN));
745 +
746 + clock_settings =
747 + vc6_phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_CK],
748 + pixel_freq);
749 + HDMI_WRITE(HDMI_TX_PHY_CTL_CK,
750 + VC4_SET_FIELD(clock_settings->ext_current_ctl,
751 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL) |
752 + VC4_SET_FIELD(clock_settings->ffe_enable,
753 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE) |
754 + VC4_SET_FIELD(clock_settings->slew_rate_ctl,
755 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL) |
756 + VC4_SET_FIELD(clock_settings->ffe_post_tap_en,
757 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN) |
758 + VC4_SET_FIELD(clock_settings->ldmos_bias_ctl,
759 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL) |
760 + VC4_SET_FIELD(clock_settings->com_mode_ldmos_en,
761 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN) |
762 + VC4_SET_FIELD(clock_settings->edge_sel,
763 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL) |
764 + VC4_SET_FIELD(clock_settings->ext_current_src_hs_en,
765 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN) |
766 + VC4_SET_FIELD(clock_settings->term_ctl,
767 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL) |
768 + VC4_SET_FIELD(clock_settings->ext_current_src_en,
769 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN) |
770 + VC4_SET_FIELD(clock_settings->int_current_src_en,
771 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN) |
772 + VC4_SET_FIELD(clock_settings->int_current_ctl,
773 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL) |
774 + VC4_SET_FIELD(clock_settings->int_current_src_hs_en,
775 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN) |
776 + VC4_SET_FIELD(clock_settings->main_tap_current_select,
777 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT) |
778 + VC4_SET_FIELD(clock_settings->post_tap_current_select,
779 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT) |
780 + VC4_SET_FIELD(clock_settings->slew_ctl_slow_loading,
781 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING) |
782 + VC4_SET_FIELD(clock_settings->slew_ctl_slow_driving,
783 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING) |
784 + VC4_SET_FIELD(clock_settings->ffe_pre_tap_en,
785 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN));
786 +
787 + if (pixel_freq >= 340000000)
788 + word_sel = 3;
789 + else
790 + word_sel = 0;
791 + HDMI_WRITE(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, word_sel);
792 +
793 + HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL,
794 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BG_PWRUP |
795 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_LDO_PWRUP |
796 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BIAS_PWRUP |
797 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_CK_PWRUP |
798 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_2_PWRUP |
799 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_1_PWRUP |
800 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_0_PWRUP);
801 +
802 + HDMI_WRITE(HDMI_TX_PHY_PLL_POWERUP_CTL,
803 + VC6_HDMI_TX_PHY_PLL_POWERUP_CTL_PLL_PWRUP);
804 +
805 + HDMI_WRITE(HDMI_TX_PHY_PLL_RESET_CTL,
806 + HDMI_READ(HDMI_TX_PHY_PLL_RESET_CTL) &
807 + ~VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_RESETB);
808 +
809 + HDMI_WRITE(HDMI_TX_PHY_PLL_RESET_CTL,
810 + HDMI_READ(HDMI_TX_PHY_PLL_RESET_CTL) |
811 + VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_RESETB);
812 +
813 + spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
814 +}
815 +
816 +void vc6_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
817 +{
818 +}
819 --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
820 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
821 @@ -111,13 +111,30 @@ enum vc4_hdmi_field {
822 HDMI_TX_PHY_CTL_1,
823 HDMI_TX_PHY_CTL_2,
824 HDMI_TX_PHY_CTL_3,
825 + HDMI_TX_PHY_CTL_CK,
826 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
827 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
828 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
829 HDMI_TX_PHY_PLL_CFG,
830 + HDMI_TX_PHY_PLL_CFG_PDIV,
831 HDMI_TX_PHY_PLL_CTL_0,
832 HDMI_TX_PHY_PLL_CTL_1,
833 + HDMI_TX_PHY_PLL_MISC_0,
834 + HDMI_TX_PHY_PLL_MISC_1,
835 + HDMI_TX_PHY_PLL_MISC_2,
836 + HDMI_TX_PHY_PLL_MISC_3,
837 + HDMI_TX_PHY_PLL_MISC_4,
838 + HDMI_TX_PHY_PLL_MISC_5,
839 + HDMI_TX_PHY_PLL_MISC_6,
840 + HDMI_TX_PHY_PLL_MISC_7,
841 + HDMI_TX_PHY_PLL_MISC_8,
842 + HDMI_TX_PHY_PLL_POST_KDIV,
843 + HDMI_TX_PHY_PLL_POWERUP_CTL,
844 + HDMI_TX_PHY_PLL_REFCLK,
845 + HDMI_TX_PHY_PLL_RESET_CTL,
846 + HDMI_TX_PHY_PLL_VCOCLK_DIV,
847 HDMI_TX_PHY_POWERDOWN_CTL,
848 + HDMI_TX_PHY_POWERUP_CTL,
849 HDMI_TX_PHY_RESET_CTL,
850 HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
851 HDMI_VEC_INTERFACE_CFG,
852 @@ -383,6 +400,206 @@ static const struct vc4_hdmi_register __
853
854 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
855 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
856 + VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
857 +
858 + VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
859 +
860 + VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
861 + VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
862 + VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
863 + VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
864 + VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
865 + VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
866 + VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
867 + VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
868 + VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
869 + VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
870 + VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
871 + VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
872 + VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
873 +
874 + VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
875 + VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
876 + VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
877 + VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
878 + VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
879 + VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
880 + VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
881 + VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
882 +};
883 +
884 +static const struct vc4_hdmi_register __maybe_unused vc6_hdmi_hdmi0_fields[] = {
885 + VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
886 + VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
887 + VC4_HD_REG(HDMI_MAI_THR, 0x0014),
888 + VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
889 + VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
890 + VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
891 + VC4_HD_REG(HDMI_VID_CTL, 0x0044),
892 + VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
893 +
894 + VC4_HDMI_REG(HDMI_FIFO_CTL, 0x07c),
895 + VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0c0),
896 + VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0c4),
897 + VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0cc),
898 + VC4_HDMI_REG(HDMI_CRP_CFG, 0x0d0),
899 + VC4_HDMI_REG(HDMI_CTS_0, 0x0d4),
900 + VC4_HDMI_REG(HDMI_CTS_1, 0x0d8),
901 + VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e8),
902 + VC4_HDMI_REG(HDMI_HORZA, 0x0ec),
903 + VC4_HDMI_REG(HDMI_HORZB, 0x0f0),
904 + VC4_HDMI_REG(HDMI_VERTA0, 0x0f4),
905 + VC4_HDMI_REG(HDMI_VERTB0, 0x0f8),
906 + VC4_HDMI_REG(HDMI_VERTA1, 0x100),
907 + VC4_HDMI_REG(HDMI_VERTB1, 0x104),
908 + VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x114),
909 + VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0a4),
910 + VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a8),
911 + VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x148),
912 + VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x14c),
913 + VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x150),
914 + VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x158),
915 + VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x15c),
916 + VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x160),
917 + VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x164),
918 + VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x168),
919 + VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x16c),
920 + VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x170),
921 + VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x18c),
922 + VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x194),
923 + VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x198),
924 + VC4_HDMI_REG(HDMI_HOTPLUG, 0x1c8),
925 + VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1e4),
926 +
927 + VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
928 + VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0f0),
929 + VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f4),
930 +
931 + VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
932 + VC5_PHY_REG(HDMI_TX_PHY_POWERUP_CTL, 0x004),
933 + VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
934 + VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
935 + VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
936 + VC5_PHY_REG(HDMI_TX_PHY_CTL_CK, 0x014),
937 + VC5_PHY_REG(HDMI_TX_PHY_PLL_REFCLK, 0x01c),
938 + VC5_PHY_REG(HDMI_TX_PHY_PLL_POST_KDIV, 0x028),
939 + VC5_PHY_REG(HDMI_TX_PHY_PLL_VCOCLK_DIV, 0x02c),
940 + VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x044),
941 + VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x054),
942 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_0, 0x060),
943 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_1, 0x064),
944 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_2, 0x068),
945 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_3, 0x06c),
946 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_4, 0x070),
947 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_5, 0x074),
948 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_6, 0x078),
949 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_7, 0x07c),
950 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_8, 0x080),
951 + VC5_PHY_REG(HDMI_TX_PHY_PLL_RESET_CTL, 0x190),
952 + VC5_PHY_REG(HDMI_TX_PHY_PLL_POWERUP_CTL, 0x194),
953 +
954 + VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
955 + VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
956 + VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
957 +
958 + VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
959 +
960 + VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
961 + VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
962 + VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
963 + VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
964 + VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
965 + VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
966 + VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
967 + VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
968 + VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
969 + VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
970 + VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
971 + VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
972 + VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
973 +
974 + VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
975 + VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
976 + VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
977 + VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
978 + VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
979 + VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
980 + VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
981 + VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
982 +};
983 +
984 +static const struct vc4_hdmi_register __maybe_unused vc6_hdmi_hdmi1_fields[] = {
985 + VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
986 + VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
987 + VC4_HD_REG(HDMI_MAI_THR, 0x0034),
988 + VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
989 + VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
990 + VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
991 + VC4_HD_REG(HDMI_VID_CTL, 0x0048),
992 + VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
993 +
994 + VC4_HDMI_REG(HDMI_FIFO_CTL, 0x07c),
995 + VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0c0),
996 + VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0c4),
997 + VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0cc),
998 + VC4_HDMI_REG(HDMI_CRP_CFG, 0x0d0),
999 + VC4_HDMI_REG(HDMI_CTS_0, 0x0d4),
1000 + VC4_HDMI_REG(HDMI_CTS_1, 0x0d8),
1001 + VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e8),
1002 + VC4_HDMI_REG(HDMI_HORZA, 0x0ec),
1003 + VC4_HDMI_REG(HDMI_HORZB, 0x0f0),
1004 + VC4_HDMI_REG(HDMI_VERTA0, 0x0f4),
1005 + VC4_HDMI_REG(HDMI_VERTB0, 0x0f8),
1006 + VC4_HDMI_REG(HDMI_VERTA1, 0x100),
1007 + VC4_HDMI_REG(HDMI_VERTB1, 0x104),
1008 + VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x114),
1009 + VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0a4),
1010 + VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a8),
1011 + VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x148),
1012 + VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x14c),
1013 + VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x150),
1014 + VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x158),
1015 + VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x15c),
1016 + VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x160),
1017 + VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x164),
1018 + VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x168),
1019 + VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x16c),
1020 + VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x170),
1021 + VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x18c),
1022 + VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x194),
1023 + VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x198),
1024 + VC4_HDMI_REG(HDMI_HOTPLUG, 0x1c8),
1025 + VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1e4),
1026 +
1027 + VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
1028 + VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0f0),
1029 + VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f4),
1030 +
1031 + VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
1032 + VC5_PHY_REG(HDMI_TX_PHY_POWERUP_CTL, 0x004),
1033 + VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
1034 + VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
1035 + VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
1036 + VC5_PHY_REG(HDMI_TX_PHY_CTL_CK, 0x014),
1037 + VC5_PHY_REG(HDMI_TX_PHY_PLL_REFCLK, 0x01c),
1038 + VC5_PHY_REG(HDMI_TX_PHY_PLL_POST_KDIV, 0x028),
1039 + VC5_PHY_REG(HDMI_TX_PHY_PLL_VCOCLK_DIV, 0x02c),
1040 + VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x044),
1041 + VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x054),
1042 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_0, 0x060),
1043 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_1, 0x064),
1044 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_2, 0x068),
1045 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_3, 0x06c),
1046 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_4, 0x070),
1047 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_5, 0x074),
1048 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_6, 0x078),
1049 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_7, 0x07c),
1050 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_8, 0x080),
1051 + VC5_PHY_REG(HDMI_TX_PHY_PLL_RESET_CTL, 0x190),
1052 + VC5_PHY_REG(HDMI_TX_PHY_PLL_POWERUP_CTL, 0x194),
1053 +
1054 + VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
1055 + VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
1056 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
1057
1058 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
Staging tree of Christian Marangi