git.openwrt.org Git - openwrt/staging/svanheule.git/blob

   1 From b1549087ecd1eb53f6173b17b473134fd6cca157 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 20 May 2022 11:22:26 +0800
   4 Subject: [PATCH 06/25] mips: mtmips: add two reference boards for mt7621
   5
   6 The mt7621_rfb board supports integrated giga PHYs plus one external
   7 giga PHYs. It also has up to 512MiB DDR3, 16MB SPI-NOR, 3 mini PCI-e x1
   8 slots, SDXC and USB.
   9
  10 The mt7621_nand_rfb board is almost the same as mt7621_rfb board, but it
  11 uses NAND flash and SDXC is not available.
  12
  13 Reviewed-by: Stefan Roese <sr@denx.de>
  14 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  15 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  16 ---
  17  arch/mips/dts/Makefile                     |  2 +
  18  arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 67 +++++++++++++++++
  19  arch/mips/dts/mediatek,mt7621-rfb.dts      | 82 +++++++++++++++++++++
  20  arch/mips/mach-mtmips/mt7621/Kconfig       | 20 +++++
  21  board/mediatek/mt7621/MAINTAINERS          |  8 ++
  22  board/mediatek/mt7621/Makefile             |  3 +
  23  board/mediatek/mt7621/board.c              |  6 ++
  24  configs/mt7621_nand_rfb_defconfig          | 85 ++++++++++++++++++++++
  25  configs/mt7621_rfb_defconfig               | 82 +++++++++++++++++++++
  26  9 files changed, 355 insertions(+)
  27  create mode 100644 arch/mips/dts/mediatek,mt7621-nand-rfb.dts
  28  create mode 100644 arch/mips/dts/mediatek,mt7621-rfb.dts
  29  create mode 100644 board/mediatek/mt7621/MAINTAINERS
  30  create mode 100644 board/mediatek/mt7621/Makefile
  31  create mode 100644 board/mediatek/mt7621/board.c
  32  create mode 100644 configs/mt7621_nand_rfb_defconfig
  33  create mode 100644 configs/mt7621_rfb_defconfig
  34
  35 diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
  36 index 95144b24dc..1b179116c9 100644
  37 --- a/arch/mips/dts/Makefile
  38 +++ b/arch/mips/dts/Makefile
  39 @@ -16,6 +16,8 @@ dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
  40  dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
  41  dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
  42  dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
  43 +dtb-$(CONFIG_BOARD_MT7621_RFB) += mediatek,mt7621-rfb.dtb
  44 +dtb-$(CONFIG_BOARD_MT7621_NAND_RFB) += mediatek,mt7621-nand-rfb.dtb
  45  dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
  46  dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
  47  dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
  48 diff --git a/arch/mips/dts/mediatek,mt7621-nand-rfb.dts b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts
  49 new file mode 100644
  50 index 0000000000..67ba298b0a
  51 --- /dev/null
  52 +++ b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts
  53 @@ -0,0 +1,67 @@
  54 +// SPDX-License-Identifier: GPL-2.0
  55 +/*
  56 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
  57 + *
  58 + * Author: Weijie Gao <weijie.gao@mediatek.com>
  59 + */
  60 +
  61 +/dts-v1/;
  62 +
  63 +#include "mt7621.dtsi"
  64 +
  65 +/ {
  66 +       compatible = "mediatek,mt7621-nand-rfb", "mediatek,mt7621-soc";
  67 +       model = "MediaTek MT7621 RFB (NAND)";
  68 +
  69 +       aliases {
  70 +               serial0 = &uart0;
  71 +       };
  72 +
  73 +       chosen {
  74 +               stdout-path = &uart0;
  75 +       };
  76 +};
  77 +
  78 +&pinctrl {
  79 +       state_default: pin_state {
  80 +               nand {
  81 +                       groups = "spi", "sdxc";
  82 +                       function = "nand";
  83 +               };
  84 +
  85 +               gpios {
  86 +                       groups = "i2c", "uart3", "pcie reset";
  87 +                       function = "gpio";
  88 +               };
  89 +
  90 +               wdt {
  91 +                       groups = "wdt";
  92 +                       function = "wdt rst";
  93 +               };
  94 +
  95 +               jtag {
  96 +                       groups = "jtag";
  97 +                       function = "jtag";
  98 +               };
  99 +       };
 100 +};
 101 +
 102 +&uart0 {
 103 +       status = "okay";
 104 +};
 105 +
 106 +&gpio {
 107 +       status = "okay";
 108 +};
 109 +
 110 +&eth {
 111 +       status = "okay";
 112 +};
 113 +
 114 +&ssusb {
 115 +       status = "okay";
 116 +};
 117 +
 118 +&u3phy {
 119 +       status = "okay";
 120 +};
 121 diff --git a/arch/mips/dts/mediatek,mt7621-rfb.dts b/arch/mips/dts/mediatek,mt7621-rfb.dts
 122 new file mode 100644
 123 index 0000000000..ff7eaf0f20
 124 --- /dev/null
 125 +++ b/arch/mips/dts/mediatek,mt7621-rfb.dts
 126 @@ -0,0 +1,82 @@
 127 +// SPDX-License-Identifier: GPL-2.0
 128 +/*
 129 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
 130 + *
 131 + * Author: Weijie Gao <weijie.gao@mediatek.com>
 132 + */
 133 +
 134 +/dts-v1/;
 135 +
 136 +#include "mt7621.dtsi"
 137 +
 138 +/ {
 139 +       compatible = "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
 140 +       model = "MediaTek MT7621 RFB (SPI-NOR)";
 141 +
 142 +       aliases {
 143 +               serial0 = &uart0;
 144 +               spi0 = &spi;
 145 +       };
 146 +
 147 +       chosen {
 148 +               stdout-path = &uart0;
 149 +       };
 150 +};
 151 +
 152 +&pinctrl {
 153 +       state_default: pin_state {
 154 +               gpios {
 155 +                       groups = "i2c", "uart3", "pcie reset";
 156 +                       function = "gpio";
 157 +               };
 158 +
 159 +               wdt {
 160 +                       groups = "wdt";
 161 +                       function = "wdt rst";
 162 +               };
 163 +
 164 +               jtag {
 165 +                       groups = "jtag";
 166 +                       function = "jtag";
 167 +               };
 168 +       };
 169 +};
 170 +
 171 +&uart0 {
 172 +       status = "okay";
 173 +};
 174 +
 175 +&gpio {
 176 +       status = "okay";
 177 +};
 178 +
 179 +&spi {
 180 +       status = "okay";
 181 +       num-cs = <2>;
 182 +
 183 +       spi-flash@0 {
 184 +               #address-cells = <1>;
 185 +               #size-cells = <1>;
 186 +               compatible = "jedec,spi-nor";
 187 +               spi-max-frequency = <25000000>;
 188 +               reg = <0>;
 189 +       };
 190 +};
 191 +
 192 +&eth {
 193 +       status = "okay";
 194 +};
 195 +
 196 +&mmc {
 197 +       cap-sd-highspeed;
 198 +
 199 +       status = "okay";
 200 +};
 201 +
 202 +&ssusb {
 203 +       status = "okay";
 204 +};
 205 +
 206 +&u3phy {
 207 +       status = "okay";
 208 +};
 209 diff --git a/arch/mips/mach-mtmips/mt7621/Kconfig b/arch/mips/mach-mtmips/mt7621/Kconfig
 210 index 37d512c68f..008a28f991 100644
 211 --- a/arch/mips/mach-mtmips/mt7621/Kconfig
 212 +++ b/arch/mips/mach-mtmips/mt7621/Kconfig
 213 @@ -79,6 +79,26 @@ config MT7621_BOOT_FROM_NAND
 214  choice
 215         prompt "Board select"
 216
 217 +config BOARD_MT7621_RFB
 218 +       bool "MediaTek MT7621 RFB (SPI-NOR)"
 219 +       help
 220 +         The reference design of MT7621A (WS3010) booting from SPI-NOR flash.
 221 +         The board can be configured with DDR2 (64MiB~256MiB) or DDR3
 222 +         (128MiB~512MiB). The board has 16 MiB SPI-NOR flash, built-in MT7530
 223 +         GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 1 SDXC, 3 PCIe
 224 +         sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out),
 225 +         JTAG pins and expansion GPIO pins.
 226 +
 227 +config BOARD_MT7621_NAND_RFB
 228 +       bool "MediaTek MT7621 RFB (NAND)"
 229 +       help
 230 +         The reference design of MT7621A (WS3010) booting from NAND flash.
 231 +         The board can be configured with DDR2 (64MiB~256MiB) or DDR3
 232 +         (128MiB~512MiB). The board has 128 MiB parallel NAND flash, built-in
 233 +         MT7530 GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 3 PCIe
 234 +         sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out),
 235 +         JTAG pins and expansion GPIO pins.
 236 +
 237  endchoice
 238
 239  config SYS_CONFIG_NAME
 240 diff --git a/board/mediatek/mt7621/MAINTAINERS b/board/mediatek/mt7621/MAINTAINERS
 241 new file mode 100644
 242 index 0000000000..f83141cea1
 243 --- /dev/null
 244 +++ b/board/mediatek/mt7621/MAINTAINERS
 245 @@ -0,0 +1,8 @@
 246 +MT7621_RFB BOARD
 247 +M:     Weijie Gao <weijie.gao@mediatek.com>
 248 +S:     Maintained
 249 +F:     board/mediatek/mt7621
 250 +F:     configs/mt7621_rfb_defconfig
 251 +F:     configs/mt7621_nand_rfb_defconfig
 252 +F:     arch/mips/dts/mediatek,mt7621-rfb.dts
 253 +F:     arch/mips/dts/mediatek,mt7621-nand-rfb.dts
 254 diff --git a/board/mediatek/mt7621/Makefile b/board/mediatek/mt7621/Makefile
 255 new file mode 100644
 256 index 0000000000..db129c5aba
 257 --- /dev/null
 258 +++ b/board/mediatek/mt7621/Makefile
 259 @@ -0,0 +1,3 @@
 260 +# SPDX-License-Identifier: GPL-2.0
 261 +
 262 +obj-y += board.o
 263 diff --git a/board/mediatek/mt7621/board.c b/board/mediatek/mt7621/board.c
 264 new file mode 100644
 265 index 0000000000..0496f3f806
 266 --- /dev/null
 267 +++ b/board/mediatek/mt7621/board.c
 268 @@ -0,0 +1,6 @@
 269 +// SPDX-License-Identifier: GPL-2.0
 270 +/*
 271 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
 272 + *
 273 + * Author: Weijie Gao <weijie.gao@mediatek.com>
 274 + */
 275 diff --git a/configs/mt7621_nand_rfb_defconfig b/configs/mt7621_nand_rfb_defconfig
 276 new file mode 100644
 277 index 0000000000..fe8543df49
 278 --- /dev/null
 279 +++ b/configs/mt7621_nand_rfb_defconfig
 280 @@ -0,0 +1,85 @@
 281 +CONFIG_MIPS=y
 282 +CONFIG_SYS_MALLOC_LEN=0x100000
 283 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
 284 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
 285 +CONFIG_NR_DRAM_BANKS=1
 286 +CONFIG_ENV_SIZE=0x1000
 287 +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-nand-rfb"
 288 +CONFIG_SPL_SERIAL=y
 289 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
 290 +CONFIG_SPL=y
 291 +CONFIG_DEBUG_UART_BASE=0xbe000c00
 292 +CONFIG_DEBUG_UART_CLOCK=50000000
 293 +CONFIG_SYS_LOAD_ADDR=0x83000000
 294 +CONFIG_ARCH_MTMIPS=y
 295 +CONFIG_SOC_MT7621=y
 296 +CONFIG_MT7621_BOOT_FROM_NAND=y
 297 +CONFIG_BOARD_MT7621_NAND_RFB=y
 298 +# CONFIG_MIPS_CACHE_SETUP is not set
 299 +# CONFIG_MIPS_CACHE_DISABLE is not set
 300 +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
 301 +CONFIG_MIPS_BOOT_FDT=y
 302 +CONFIG_DEBUG_UART=y
 303 +CONFIG_FIT=y
 304 +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 305 +CONFIG_SYS_CONSOLE_INFO_QUIET=y
 306 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 307 +CONFIG_SPL_NAND_SUPPORT=y
 308 +CONFIG_SPL_NAND_BASE=y
 309 +CONFIG_SPL_NAND_IDENT=y
 310 +# CONFIG_BOOTM_NETBSD is not set
 311 +# CONFIG_BOOTM_PLAN9 is not set
 312 +# CONFIG_BOOTM_RTEMS is not set
 313 +# CONFIG_BOOTM_VXWORKS is not set
 314 +# CONFIG_CMD_ELF is not set
 315 +# CONFIG_CMD_XIMG is not set
 316 +# CONFIG_CMD_CRC32 is not set
 317 +# CONFIG_CMD_DM is not set
 318 +# CONFIG_CMD_FLASH is not set
 319 +CONFIG_CMD_GPIO=y
 320 +# CONFIG_CMD_LOADS is not set
 321 +CONFIG_CMD_MMC=y
 322 +CONFIG_CMD_MTD=y
 323 +CONFIG_CMD_PART=y
 324 +# CONFIG_CMD_PINMUX is not set
 325 +CONFIG_CMD_USB=y
 326 +# CONFIG_CMD_NFS is not set
 327 +CONFIG_CMD_FAT=y
 328 +CONFIG_CMD_FS_GENERIC=y
 329 +# CONFIG_SPL_DOS_PARTITION is not set
 330 +# CONFIG_ISO_PARTITION is not set
 331 +CONFIG_EFI_PARTITION=y
 332 +# CONFIG_SPL_EFI_PARTITION is not set
 333 +CONFIG_PARTITION_TYPE_GUID=y
 334 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 335 +CONFIG_NET_RANDOM_ETHADDR=y
 336 +# CONFIG_I2C is not set
 337 +# CONFIG_INPUT is not set
 338 +CONFIG_MMC=y
 339 +# CONFIG_MMC_QUIRKS is not set
 340 +# CONFIG_MMC_HW_PARTITIONING is not set
 341 +CONFIG_MMC_MTK=y
 342 +CONFIG_MTD=y
 343 +CONFIG_DM_MTD=y
 344 +CONFIG_MTD_RAW_NAND=y
 345 +CONFIG_NAND_MT7621=y
 346 +CONFIG_SYS_NAND_ONFI_DETECTION=y
 347 +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 348 +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
 349 +CONFIG_MEDIATEK_ETH=y
 350 +CONFIG_PHY=y
 351 +CONFIG_PHY_MTK_TPHY=y
 352 +CONFIG_DEBUG_UART_SHIFT=2
 353 +CONFIG_SYSRESET=y
 354 +CONFIG_SYSRESET_RESETCTL=y
 355 +CONFIG_USB=y
 356 +CONFIG_USB_XHCI_HCD=y
 357 +CONFIG_USB_XHCI_MTK=y
 358 +CONFIG_USB_STORAGE=y
 359 +CONFIG_WDT=y
 360 +CONFIG_WDT_MT7621=y
 361 +CONFIG_FAT_WRITE=y
 362 +# CONFIG_BINMAN_FDT is not set
 363 +CONFIG_LZMA=y
 364 +# CONFIG_GZIP is not set
 365 +CONFIG_SPL_LZMA=y
 366 diff --git a/configs/mt7621_rfb_defconfig b/configs/mt7621_rfb_defconfig
 367 new file mode 100644
 368 index 0000000000..ae62360e63
 369 --- /dev/null
 370 +++ b/configs/mt7621_rfb_defconfig
 371 @@ -0,0 +1,82 @@
 372 +CONFIG_MIPS=y
 373 +CONFIG_SYS_MALLOC_LEN=0x100000
 374 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
 375 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
 376 +CONFIG_NR_DRAM_BANKS=1
 377 +CONFIG_ENV_SIZE=0x1000
 378 +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-rfb"
 379 +CONFIG_SPL_SERIAL=y
 380 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
 381 +CONFIG_SPL=y
 382 +CONFIG_DEBUG_UART_BASE=0xbe000c00
 383 +CONFIG_DEBUG_UART_CLOCK=50000000
 384 +CONFIG_SYS_LOAD_ADDR=0x83000000
 385 +CONFIG_ARCH_MTMIPS=y
 386 +CONFIG_SOC_MT7621=y
 387 +# CONFIG_MIPS_CACHE_SETUP is not set
 388 +# CONFIG_MIPS_CACHE_DISABLE is not set
 389 +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
 390 +CONFIG_MIPS_BOOT_FDT=y
 391 +CONFIG_DEBUG_UART=y
 392 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
 393 +CONFIG_FIT=y
 394 +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 395 +CONFIG_SYS_CONSOLE_INFO_QUIET=y
 396 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 397 +CONFIG_SPL_NOR_SUPPORT=y
 398 +CONFIG_TPL=y
 399 +# CONFIG_TPL_FRAMEWORK is not set
 400 +# CONFIG_BOOTM_NETBSD is not set
 401 +# CONFIG_BOOTM_PLAN9 is not set
 402 +# CONFIG_BOOTM_RTEMS is not set
 403 +# CONFIG_BOOTM_VXWORKS is not set
 404 +# CONFIG_CMD_ELF is not set
 405 +# CONFIG_CMD_XIMG is not set
 406 +# CONFIG_CMD_CRC32 is not set
 407 +# CONFIG_CMD_DM is not set
 408 +CONFIG_CMD_GPIO=y
 409 +# CONFIG_CMD_LOADS is not set
 410 +CONFIG_CMD_MMC=y
 411 +CONFIG_CMD_PART=y
 412 +# CONFIG_CMD_PINMUX is not set
 413 +CONFIG_CMD_SPI=y
 414 +# CONFIG_CMD_NFS is not set
 415 +CONFIG_DOS_PARTITION=y
 416 +# CONFIG_SPL_DOS_PARTITION is not set
 417 +# CONFIG_ISO_PARTITION is not set
 418 +CONFIG_EFI_PARTITION=y
 419 +# CONFIG_SPL_EFI_PARTITION is not set
 420 +CONFIG_PARTITION_TYPE_GUID=y
 421 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 422 +CONFIG_NET_RANDOM_ETHADDR=y
 423 +# CONFIG_I2C is not set
 424 +# CONFIG_INPUT is not set
 425 +CONFIG_MMC=y
 426 +# CONFIG_MMC_QUIRKS is not set
 427 +# CONFIG_MMC_HW_PARTITIONING is not set
 428 +CONFIG_MMC_MTK=y
 429 +CONFIG_SF_DEFAULT_SPEED=20000000
 430 +CONFIG_SPI_FLASH_BAR=y
 431 +CONFIG_SPI_FLASH_EON=y
 432 +CONFIG_SPI_FLASH_GIGADEVICE=y
 433 +CONFIG_SPI_FLASH_ISSI=y
 434 +CONFIG_SPI_FLASH_MACRONIX=y
 435 +CONFIG_SPI_FLASH_SPANSION=y
 436 +CONFIG_SPI_FLASH_STMICRO=y
 437 +CONFIG_SPI_FLASH_WINBOND=y
 438 +CONFIG_SPI_FLASH_XMC=y
 439 +CONFIG_SPI_FLASH_XTX=y
 440 +CONFIG_MEDIATEK_ETH=y
 441 +CONFIG_PHY=y
 442 +CONFIG_PHY_MTK_TPHY=y
 443 +CONFIG_DEBUG_UART_SHIFT=2
 444 +CONFIG_SPI=y
 445 +CONFIG_MT7621_SPI=y
 446 +CONFIG_SYSRESET=y
 447 +CONFIG_SYSRESET_RESETCTL=y
 448 +CONFIG_WDT=y
 449 +CONFIG_WDT_MT7621=y
 450 +# CONFIG_BINMAN_FDT is not set
 451 +CONFIG_LZMA=y
 452 +# CONFIG_GZIP is not set
 453 +CONFIG_SPL_LZMA=y
 454 --
 455 2.36.1
 456