projects / openwrt / staging / stintel.git / blob
? search:


d99ac9992f3bfcbb41d6119f75d9a938d8301204
[openwrt/staging/stintel.git] /
1 From cb02866f9a740fb9fb8ff19698a69290da4057e5 Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Sat, 26 Feb 2022 14:52:25 +0100
4 Subject: [PATCH 05/14] clk: qcom: gcc-ipq806x: convert parent_names to
5 parent_data
6
7 Convert parent_names to parent_data to modernize the driver.
8 Where possible use parent_hws directly.
9
10 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
11 Tested-by: Jonathan McDowell <noodles@earth.li>
12 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
13 Link: https://lore.kernel.org/r/20220226135235.10051-6-ansuelsmth@gmail.com
14 ---
15 drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++-------------
16 1 file changed, 173 insertions(+), 113 deletions(-)
17
18 --- a/drivers/clk/qcom/gcc-ipq806x.c
19 +++ b/drivers/clk/qcom/gcc-ipq806x.c
20 @@ -25,6 +25,10 @@
21 #include "clk-hfpll.h"
22 #include "reset.h"
23
24 +static const struct clk_parent_data gcc_pxo[] = {
25 + { .fw_name = "pxo", .name = "pxo" },
26 +};
27 +
28 static struct clk_pll pll0 = {
29 .l_reg = 0x30c4,
30 .m_reg = 0x30c8,
31 @@ -35,7 +39,7 @@ static struct clk_pll pll0 = {
32 .status_bit = 16,
33 .clkr.hw.init = &(struct clk_init_data){
34 .name = "pll0",
35 - .parent_names = (const char *[]){ "pxo" },
36 + .parent_data = gcc_pxo,
37 .num_parents = 1,
38 .ops = &clk_pll_ops,
39 },
40 @@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = {
41 .enable_mask = BIT(0),
42 .hw.init = &(struct clk_init_data){
43 .name = "pll0_vote",
44 - .parent_names = (const char *[]){ "pll0" },
45 + .parent_hws = (const struct clk_hw*[]){
46 + &pll0.clkr.hw,
47 + },
48 .num_parents = 1,
49 .ops = &clk_pll_vote_ops,
50 },
51 @@ -62,7 +68,7 @@ static struct clk_pll pll3 = {
52 .status_bit = 16,
53 .clkr.hw.init = &(struct clk_init_data){
54 .name = "pll3",
55 - .parent_names = (const char *[]){ "pxo" },
56 + .parent_data = gcc_pxo,
57 .num_parents = 1,
58 .ops = &clk_pll_ops,
59 },
60 @@ -89,7 +95,7 @@ static struct clk_pll pll8 = {
61 .status_bit = 16,
62 .clkr.hw.init = &(struct clk_init_data){
63 .name = "pll8",
64 - .parent_names = (const char *[]){ "pxo" },
65 + .parent_data = gcc_pxo,
66 .num_parents = 1,
67 .ops = &clk_pll_ops,
68 },
69 @@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = {
70 .enable_mask = BIT(8),
71 .hw.init = &(struct clk_init_data){
72 .name = "pll8_vote",
73 - .parent_names = (const char *[]){ "pll8" },
74 + .parent_hws = (const struct clk_hw*[]){
75 + &pll8.clkr.hw,
76 + },
77 .num_parents = 1,
78 .ops = &clk_pll_vote_ops,
79 },
80 @@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = {
81 static struct clk_hfpll hfpll0 = {
82 .d = &hfpll0_data,
83 .clkr.hw.init = &(struct clk_init_data){
84 - .parent_names = (const char *[]){ "pxo" },
85 + .parent_data = gcc_pxo,
86 .num_parents = 1,
87 .name = "hfpll0",
88 .ops = &clk_ops_hfpll,
89 @@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = {
90 static struct clk_hfpll hfpll1 = {
91 .d = &hfpll1_data,
92 .clkr.hw.init = &(struct clk_init_data){
93 - .parent_names = (const char *[]){ "pxo" },
94 + .parent_data = gcc_pxo,
95 .num_parents = 1,
96 .name = "hfpll1",
97 .ops = &clk_ops_hfpll,
98 @@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data =
99 static struct clk_hfpll hfpll_l2 = {
100 .d = &hfpll_l2_data,
101 .clkr.hw.init = &(struct clk_init_data){
102 - .parent_names = (const char *[]){ "pxo" },
103 + .parent_data = gcc_pxo,
104 .num_parents = 1,
105 .name = "hfpll_l2",
106 .ops = &clk_ops_hfpll,
107 @@ -194,7 +202,7 @@ static struct clk_pll pll14 = {
108 .status_bit = 16,
109 .clkr.hw.init = &(struct clk_init_data){
110 .name = "pll14",
111 - .parent_names = (const char *[]){ "pxo" },
112 + .parent_data = gcc_pxo,
113 .num_parents = 1,
114 .ops = &clk_pll_ops,
115 },
116 @@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = {
117 .enable_mask = BIT(14),
118 .hw.init = &(struct clk_init_data){
119 .name = "pll14_vote",
120 - .parent_names = (const char *[]){ "pll14" },
121 + .parent_hws = (const struct clk_hw*[]){
122 + &pll14.clkr.hw,
123 + },
124 .num_parents = 1,
125 .ops = &clk_pll_vote_ops,
126 },
127 @@ -238,7 +248,7 @@ static struct clk_pll pll18 = {
128 .freq_tbl = pll18_freq_tbl,
129 .clkr.hw.init = &(struct clk_init_data){
130 .name = "pll18",
131 - .parent_names = (const char *[]){ "pxo" },
132 + .parent_data = gcc_pxo,
133 .num_parents = 1,
134 .ops = &clk_pll_ops,
135 },
136 @@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_p
137 { P_PLL8, 3 }
138 };
139
140 -static const char * const gcc_pxo_pll8[] = {
141 - "pxo",
142 - "pll8_vote",
143 +static const struct clk_parent_data gcc_pxo_pll8[] = {
144 + { .fw_name = "pxo", .name = "pxo" },
145 + { .hw = &pll8_vote.hw },
146 };
147
148 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
149 @@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_p
150 { P_CXO, 5 }
151 };
152
153 -static const char * const gcc_pxo_pll8_cxo[] = {
154 - "pxo",
155 - "pll8_vote",
156 - "cxo",
157 +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
158 + { .fw_name = "pxo", .name = "pxo" },
159 + { .hw = &pll8_vote.hw },
160 + { .fw_name = "cxo", .name = "cxo" },
161 };
162
163 static const struct parent_map gcc_pxo_pll3_map[] = {
164 @@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_p
165 { P_PLL3, 6 }
166 };
167
168 -static const char * const gcc_pxo_pll3[] = {
169 - "pxo",
170 - "pll3",
171 +static const struct clk_parent_data gcc_pxo_pll3[] = {
172 + { .fw_name = "pxo", .name = "pxo" },
173 + { .hw = &pll3.clkr.hw },
174 };
175
176 static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
177 @@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_p
178 { P_PLL0, 2 }
179 };
180
181 -static const char * const gcc_pxo_pll8_pll0[] = {
182 - "pxo",
183 - "pll8_vote",
184 - "pll0_vote",
185 +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
186 + { .fw_name = "pxo", .name = "pxo" },
187 + { .hw = &pll8_vote.hw },
188 + { .hw = &pll0_vote.hw },
189 };
190
191 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
192 @@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_p
193 { P_PLL18, 1 }
194 };
195
196 -static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
197 - "pxo",
198 - "pll8_vote",
199 - "pll0_vote",
200 - "pll14",
201 - "pll18",
202 +static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
203 + { .fw_name = "pxo", .name = "pxo" },
204 + { .hw = &pll8_vote.hw },
205 + { .hw = &pll0_vote.hw },
206 + { .hw = &pll14.clkr.hw },
207 + { .hw = &pll18.clkr.hw },
208 };
209
210 static struct freq_tbl clk_tbl_gsbi_uart[] = {
211 @@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = {
212 .enable_mask = BIT(11),
213 .hw.init = &(struct clk_init_data){
214 .name = "gsbi1_uart_src",
215 - .parent_names = gcc_pxo_pll8,
216 + .parent_data = gcc_pxo_pll8,
217 .num_parents = 2,
218 .ops = &clk_rcg_ops,
219 .flags = CLK_SET_PARENT_GATE,
220 @@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk
221 .enable_mask = BIT(9),
222 .hw.init = &(struct clk_init_data){
223 .name = "gsbi1_uart_clk",
224 - .parent_names = (const char *[]){
225 - "gsbi1_uart_src",
226 + .parent_hws = (const struct clk_hw*[]){
227 + &gsbi1_uart_src.clkr.hw,
228 },
229 .num_parents = 1,
230 .ops = &clk_branch_ops,
231 @@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = {
232 .enable_mask = BIT(11),
233 .hw.init = &(struct clk_init_data){
234 .name = "gsbi2_uart_src",
235 - .parent_names = gcc_pxo_pll8,
236 + .parent_data = gcc_pxo_pll8,
237 .num_parents = 2,
238 .ops = &clk_rcg_ops,
239 .flags = CLK_SET_PARENT_GATE,
240 @@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk
241 .enable_mask = BIT(9),
242 .hw.init = &(struct clk_init_data){
243 .name = "gsbi2_uart_clk",
244 - .parent_names = (const char *[]){
245 - "gsbi2_uart_src",
246 + .parent_hws = (const struct clk_hw*[]){
247 + &gsbi2_uart_src.clkr.hw,
248 },
249 .num_parents = 1,
250 .ops = &clk_branch_ops,
251 @@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = {
252 .enable_mask = BIT(11),
253 .hw.init = &(struct clk_init_data){
254 .name = "gsbi4_uart_src",
255 - .parent_names = gcc_pxo_pll8,
256 + .parent_data = gcc_pxo_pll8,
257 .num_parents = 2,
258 .ops = &clk_rcg_ops,
259 .flags = CLK_SET_PARENT_GATE,
260 @@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk
261 .enable_mask = BIT(9),
262 .hw.init = &(struct clk_init_data){
263 .name = "gsbi4_uart_clk",
264 - .parent_names = (const char *[]){
265 - "gsbi4_uart_src",
266 + .parent_hws = (const struct clk_hw*[]){
267 + &gsbi4_uart_src.clkr.hw,
268 },
269 .num_parents = 1,
270 .ops = &clk_branch_ops,
271 @@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = {
272 .enable_mask = BIT(11),
273 .hw.init = &(struct clk_init_data){
274 .name = "gsbi5_uart_src",
275 - .parent_names = gcc_pxo_pll8,
276 + .parent_data = gcc_pxo_pll8,
277 .num_parents = 2,
278 .ops = &clk_rcg_ops,
279 .flags = CLK_SET_PARENT_GATE,
280 @@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk
281 .enable_mask = BIT(9),
282 .hw.init = &(struct clk_init_data){
283 .name = "gsbi5_uart_clk",
284 - .parent_names = (const char *[]){
285 - "gsbi5_uart_src",
286 + .parent_hws = (const struct clk_hw*[]){
287 + &gsbi5_uart_src.clkr.hw,
288 },
289 .num_parents = 1,
290 .ops = &clk_branch_ops,
291 @@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = {
292 .enable_mask = BIT(11),
293 .hw.init = &(struct clk_init_data){
294 .name = "gsbi6_uart_src",
295 - .parent_names = gcc_pxo_pll8,
296 + .parent_data = gcc_pxo_pll8,
297 .num_parents = 2,
298 .ops = &clk_rcg_ops,
299 .flags = CLK_SET_PARENT_GATE,
300 @@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk
301 .enable_mask = BIT(9),
302 .hw.init = &(struct clk_init_data){
303 .name = "gsbi6_uart_clk",
304 - .parent_names = (const char *[]){
305 - "gsbi6_uart_src",
306 + .parent_hws = (const struct clk_hw*[]){
307 + &gsbi6_uart_src.clkr.hw,
308 },
309 .num_parents = 1,
310 .ops = &clk_branch_ops,
311 @@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = {
312 .enable_mask = BIT(11),
313 .hw.init = &(struct clk_init_data){
314 .name = "gsbi7_uart_src",
315 - .parent_names = gcc_pxo_pll8,
316 + .parent_data = gcc_pxo_pll8,
317 .num_parents = 2,
318 .ops = &clk_rcg_ops,
319 .flags = CLK_SET_PARENT_GATE,
320 @@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk
321 .enable_mask = BIT(9),
322 .hw.init = &(struct clk_init_data){
323 .name = "gsbi7_uart_clk",
324 - .parent_names = (const char *[]){
325 - "gsbi7_uart_src",
326 + .parent_hws = (const struct clk_hw*[]){
327 + &gsbi7_uart_src.clkr.hw,
328 },
329 .num_parents = 1,
330 .ops = &clk_branch_ops,
331 @@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = {
332 .enable_mask = BIT(11),
333 .hw.init = &(struct clk_init_data){
334 .name = "gsbi1_qup_src",
335 - .parent_names = gcc_pxo_pll8,
336 + .parent_data = gcc_pxo_pll8,
337 .num_parents = 2,
338 .ops = &clk_rcg_ops,
339 .flags = CLK_SET_PARENT_GATE,
340 @@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk =
341 .enable_mask = BIT(9),
342 .hw.init = &(struct clk_init_data){
343 .name = "gsbi1_qup_clk",
344 - .parent_names = (const char *[]){ "gsbi1_qup_src" },
345 + .parent_hws = (const struct clk_hw*[]){
346 + &gsbi1_qup_src.clkr.hw,
347 + },
348 .num_parents = 1,
349 .ops = &clk_branch_ops,
350 .flags = CLK_SET_RATE_PARENT,
351 @@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = {
352 .enable_mask = BIT(11),
353 .hw.init = &(struct clk_init_data){
354 .name = "gsbi2_qup_src",
355 - .parent_names = gcc_pxo_pll8,
356 + .parent_data = gcc_pxo_pll8,
357 .num_parents = 2,
358 .ops = &clk_rcg_ops,
359 .flags = CLK_SET_PARENT_GATE,
360 @@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk =
361 .enable_mask = BIT(9),
362 .hw.init = &(struct clk_init_data){
363 .name = "gsbi2_qup_clk",
364 - .parent_names = (const char *[]){ "gsbi2_qup_src" },
365 + .parent_hws = (const struct clk_hw*[]){
366 + &gsbi2_qup_src.clkr.hw,
367 + },
368 .num_parents = 1,
369 .ops = &clk_branch_ops,
370 .flags = CLK_SET_RATE_PARENT,
371 @@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = {
372 .enable_mask = BIT(11),
373 .hw.init = &(struct clk_init_data){
374 .name = "gsbi4_qup_src",
375 - .parent_names = gcc_pxo_pll8,
376 + .parent_data = gcc_pxo_pll8,
377 .num_parents = 2,
378 .ops = &clk_rcg_ops,
379 .flags = CLK_SET_PARENT_GATE,
380 @@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk =
381 .enable_mask = BIT(9),
382 .hw.init = &(struct clk_init_data){
383 .name = "gsbi4_qup_clk",
384 - .parent_names = (const char *[]){ "gsbi4_qup_src" },
385 + .parent_hws = (const struct clk_hw*[]){
386 + &gsbi4_qup_src.clkr.hw,
387 + },
388 .num_parents = 1,
389 .ops = &clk_branch_ops,
390 .flags = CLK_SET_RATE_PARENT,
391 @@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = {
392 .enable_mask = BIT(11),
393 .hw.init = &(struct clk_init_data){
394 .name = "gsbi5_qup_src",
395 - .parent_names = gcc_pxo_pll8,
396 + .parent_data = gcc_pxo_pll8,
397 .num_parents = 2,
398 .ops = &clk_rcg_ops,
399 .flags = CLK_SET_PARENT_GATE,
400 @@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk =
401 .enable_mask = BIT(9),
402 .hw.init = &(struct clk_init_data){
403 .name = "gsbi5_qup_clk",
404 - .parent_names = (const char *[]){ "gsbi5_qup_src" },
405 + .parent_hws = (const struct clk_hw*[]){
406 + &gsbi5_qup_src.clkr.hw,
407 + },
408 .num_parents = 1,
409 .ops = &clk_branch_ops,
410 .flags = CLK_SET_RATE_PARENT,
411 @@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = {
412 .enable_mask = BIT(11),
413 .hw.init = &(struct clk_init_data){
414 .name = "gsbi6_qup_src",
415 - .parent_names = gcc_pxo_pll8,
416 + .parent_data = gcc_pxo_pll8,
417 .num_parents = 2,
418 .ops = &clk_rcg_ops,
419 .flags = CLK_SET_PARENT_GATE,
420 @@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk =
421 .enable_mask = BIT(9),
422 .hw.init = &(struct clk_init_data){
423 .name = "gsbi6_qup_clk",
424 - .parent_names = (const char *[]){ "gsbi6_qup_src" },
425 + .parent_hws = (const struct clk_hw*[]){
426 + &gsbi6_qup_src.clkr.hw,
427 + },
428 .num_parents = 1,
429 .ops = &clk_branch_ops,
430 .flags = CLK_SET_RATE_PARENT,
431 @@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = {
432 .enable_mask = BIT(11),
433 .hw.init = &(struct clk_init_data){
434 .name = "gsbi7_qup_src",
435 - .parent_names = gcc_pxo_pll8,
436 + .parent_data = gcc_pxo_pll8,
437 .num_parents = 2,
438 .ops = &clk_rcg_ops,
439 .flags = CLK_SET_PARENT_GATE,
440 @@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk =
441 .enable_mask = BIT(9),
442 .hw.init = &(struct clk_init_data){
443 .name = "gsbi7_qup_clk",
444 - .parent_names = (const char *[]){ "gsbi7_qup_src" },
445 + .parent_hws = (const struct clk_hw*[]){
446 + &gsbi7_qup_src.clkr.hw,
447 + },
448 .num_parents = 1,
449 .ops = &clk_branch_ops,
450 .flags = CLK_SET_RATE_PARENT,
451 @@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = {
452 .enable_mask = BIT(11),
453 .hw.init = &(struct clk_init_data){
454 .name = "gp0_src",
455 - .parent_names = gcc_pxo_pll8_cxo,
456 + .parent_data = gcc_pxo_pll8_cxo,
457 .num_parents = 3,
458 .ops = &clk_rcg_ops,
459 .flags = CLK_SET_PARENT_GATE,
460 @@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = {
461 .enable_mask = BIT(9),
462 .hw.init = &(struct clk_init_data){
463 .name = "gp0_clk",
464 - .parent_names = (const char *[]){ "gp0_src" },
465 + .parent_hws = (const struct clk_hw*[]){
466 + &gp0_src.clkr.hw,
467 + },
468 .num_parents = 1,
469 .ops = &clk_branch_ops,
470 .flags = CLK_SET_RATE_PARENT,
471 @@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = {
472 .enable_mask = BIT(11),
473 .hw.init = &(struct clk_init_data){
474 .name = "gp1_src",
475 - .parent_names = gcc_pxo_pll8_cxo,
476 + .parent_data = gcc_pxo_pll8_cxo,
477 .num_parents = 3,
478 .ops = &clk_rcg_ops,
479 .flags = CLK_SET_RATE_GATE,
480 @@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = {
481 .enable_mask = BIT(9),
482 .hw.init = &(struct clk_init_data){
483 .name = "gp1_clk",
484 - .parent_names = (const char *[]){ "gp1_src" },
485 + .parent_hws = (const struct clk_hw*[]){
486 + &gp1_src.clkr.hw,
487 + },
488 .num_parents = 1,
489 .ops = &clk_branch_ops,
490 .flags = CLK_SET_RATE_PARENT,
491 @@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = {
492 .enable_mask = BIT(11),
493 .hw.init = &(struct clk_init_data){
494 .name = "gp2_src",
495 - .parent_names = gcc_pxo_pll8_cxo,
496 + .parent_data = gcc_pxo_pll8_cxo,
497 .num_parents = 3,
498 .ops = &clk_rcg_ops,
499 .flags = CLK_SET_RATE_GATE,
500 @@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = {
501 .enable_mask = BIT(9),
502 .hw.init = &(struct clk_init_data){
503 .name = "gp2_clk",
504 - .parent_names = (const char *[]){ "gp2_src" },
505 + .parent_hws = (const struct clk_hw*[]){
506 + &gp2_src.clkr.hw,
507 + },
508 .num_parents = 1,
509 .ops = &clk_branch_ops,
510 .flags = CLK_SET_RATE_PARENT,
511 @@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = {
512 .enable_mask = BIT(11),
513 .hw.init = &(struct clk_init_data){
514 .name = "prng_src",
515 - .parent_names = gcc_pxo_pll8,
516 + .parent_data = gcc_pxo_pll8,
517 .num_parents = 2,
518 .ops = &clk_rcg_ops,
519 },
520 @@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = {
521 .enable_mask = BIT(10),
522 .hw.init = &(struct clk_init_data){
523 .name = "prng_clk",
524 - .parent_names = (const char *[]){ "prng_src" },
525 + .parent_hws = (const struct clk_hw*[]){
526 + &prng_src.clkr.hw,
527 + },
528 .num_parents = 1,
529 .ops = &clk_branch_ops,
530 },
531 @@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = {
532 .enable_mask = BIT(11),
533 .hw.init = &(struct clk_init_data){
534 .name = "sdc1_src",
535 - .parent_names = gcc_pxo_pll8,
536 + .parent_data = gcc_pxo_pll8,
537 .num_parents = 2,
538 .ops = &clk_rcg_ops,
539 },
540 @@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = {
541 .enable_mask = BIT(9),
542 .hw.init = &(struct clk_init_data){
543 .name = "sdc1_clk",
544 - .parent_names = (const char *[]){ "sdc1_src" },
545 + .parent_hws = (const struct clk_hw*[]){
546 + &sdc1_src.clkr.hw,
547 + },
548 .num_parents = 1,
549 .ops = &clk_branch_ops,
550 .flags = CLK_SET_RATE_PARENT,
551 @@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = {
552 .enable_mask = BIT(11),
553 .hw.init = &(struct clk_init_data){
554 .name = "sdc3_src",
555 - .parent_names = gcc_pxo_pll8,
556 + .parent_data = gcc_pxo_pll8,
557 .num_parents = 2,
558 .ops = &clk_rcg_ops,
559 },
560 @@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = {
561 .enable_mask = BIT(9),
562 .hw.init = &(struct clk_init_data){
563 .name = "sdc3_clk",
564 - .parent_names = (const char *[]){ "sdc3_src" },
565 + .parent_hws = (const struct clk_hw*[]){
566 + &sdc3_src.clkr.hw,
567 + },
568 .num_parents = 1,
569 .ops = &clk_branch_ops,
570 .flags = CLK_SET_RATE_PARENT,
571 @@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = {
572 .enable_mask = BIT(11),
573 .hw.init = &(struct clk_init_data){
574 .name = "tsif_ref_src",
575 - .parent_names = gcc_pxo_pll8,
576 + .parent_data = gcc_pxo_pll8,
577 .num_parents = 2,
578 .ops = &clk_rcg_ops,
579 },
580 @@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk =
581 .enable_mask = BIT(9),
582 .hw.init = &(struct clk_init_data){
583 .name = "tsif_ref_clk",
584 - .parent_names = (const char *[]){ "tsif_ref_src" },
585 + .parent_hws = (const struct clk_hw*[]){
586 + &tsif_ref_src.clkr.hw,
587 + },
588 .num_parents = 1,
589 .ops = &clk_branch_ops,
590 .flags = CLK_SET_RATE_PARENT,
591 @@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = {
592 .enable_mask = BIT(11),
593 .hw.init = &(struct clk_init_data){
594 .name = "pcie_ref_src",
595 - .parent_names = gcc_pxo_pll3,
596 + .parent_data = gcc_pxo_pll3,
597 .num_parents = 2,
598 .ops = &clk_rcg_ops,
599 .flags = CLK_SET_RATE_GATE,
600 @@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_cl
601 .enable_mask = BIT(9),
602 .hw.init = &(struct clk_init_data){
603 .name = "pcie_ref_src_clk",
604 - .parent_names = (const char *[]){ "pcie_ref_src" },
605 + .parent_hws = (const struct clk_hw*[]){
606 + &pcie_ref_src.clkr.hw,
607 + },
608 .num_parents = 1,
609 .ops = &clk_branch_ops,
610 .flags = CLK_SET_RATE_PARENT,
611 @@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = {
612 .enable_mask = BIT(11),
613 .hw.init = &(struct clk_init_data){
614 .name = "pcie1_ref_src",
615 - .parent_names = gcc_pxo_pll3,
616 + .parent_data = gcc_pxo_pll3,
617 .num_parents = 2,
618 .ops = &clk_rcg_ops,
619 .flags = CLK_SET_RATE_GATE,
620 @@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_c
621 .enable_mask = BIT(9),
622 .hw.init = &(struct clk_init_data){
623 .name = "pcie1_ref_src_clk",
624 - .parent_names = (const char *[]){ "pcie1_ref_src" },
625 + .parent_hws = (const struct clk_hw*[]){
626 + &pcie1_ref_src.clkr.hw,
627 + },
628 .num_parents = 1,
629 .ops = &clk_branch_ops,
630 .flags = CLK_SET_RATE_PARENT,
631 @@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = {
632 .enable_mask = BIT(11),
633 .hw.init = &(struct clk_init_data){
634 .name = "pcie2_ref_src",
635 - .parent_names = gcc_pxo_pll3,
636 + .parent_data = gcc_pxo_pll3,
637 .num_parents = 2,
638 .ops = &clk_rcg_ops,
639 .flags = CLK_SET_RATE_GATE,
640 @@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_c
641 .enable_mask = BIT(9),
642 .hw.init = &(struct clk_init_data){
643 .name = "pcie2_ref_src_clk",
644 - .parent_names = (const char *[]){ "pcie2_ref_src" },
645 + .parent_hws = (const struct clk_hw*[]){
646 + &pcie2_ref_src.clkr.hw,
647 + },
648 .num_parents = 1,
649 .ops = &clk_branch_ops,
650 .flags = CLK_SET_RATE_PARENT,
651 @@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = {
652 .enable_mask = BIT(7),
653 .hw.init = &(struct clk_init_data){
654 .name = "sata_ref_src",
655 - .parent_names = gcc_pxo_pll3,
656 + .parent_data = gcc_pxo_pll3,
657 .num_parents = 2,
658 .ops = &clk_rcg_ops,
659 .flags = CLK_SET_RATE_GATE,
660 @@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk
661 .enable_mask = BIT(4),
662 .hw.init = &(struct clk_init_data){
663 .name = "sata_rxoob_clk",
664 - .parent_names = (const char *[]){ "sata_ref_src" },
665 + .parent_hws = (const struct clk_hw*[]){
666 + &sata_ref_src.clkr.hw,
667 + },
668 .num_parents = 1,
669 .ops = &clk_branch_ops,
670 .flags = CLK_SET_RATE_PARENT,
671 @@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_cl
672 .enable_mask = BIT(4),
673 .hw.init = &(struct clk_init_data){
674 .name = "sata_pmalive_clk",
675 - .parent_names = (const char *[]){ "sata_ref_src" },
676 + .parent_hws = (const struct clk_hw*[]){
677 + &sata_ref_src.clkr.hw,
678 + },
679 .num_parents = 1,
680 .ops = &clk_branch_ops,
681 .flags = CLK_SET_RATE_PARENT,
682 @@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_cl
683 .enable_mask = BIT(4),
684 .hw.init = &(struct clk_init_data){
685 .name = "sata_phy_ref_clk",
686 - .parent_names = (const char *[]){ "pxo" },
687 + .parent_data = gcc_pxo,
688 .num_parents = 1,
689 .ops = &clk_branch_ops,
690 },
691 @@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_s
692 .enable_mask = BIT(11),
693 .hw.init = &(struct clk_init_data){
694 .name = "usb30_master_ref_src",
695 - .parent_names = gcc_pxo_pll8_pll0,
696 + .parent_data = gcc_pxo_pll8_pll0,
697 .num_parents = 3,
698 .ops = &clk_rcg_ops,
699 .flags = CLK_SET_RATE_GATE,
700 @@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_
701 .enable_mask = BIT(4),
702 .hw.init = &(struct clk_init_data){
703 .name = "usb30_0_branch_clk",
704 - .parent_names = (const char *[]){ "usb30_master_ref_src", },
705 + .parent_hws = (const struct clk_hw*[]){
706 + &usb30_master_clk_src.clkr.hw,
707 + },
708 .num_parents = 1,
709 .ops = &clk_branch_ops,
710 .flags = CLK_SET_RATE_PARENT,
711 @@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_
712 .enable_mask = BIT(4),
713 .hw.init = &(struct clk_init_data){
714 .name = "usb30_1_branch_clk",
715 - .parent_names = (const char *[]){ "usb30_master_ref_src", },
716 + .parent_hws = (const struct clk_hw*[]){
717 + &usb30_master_clk_src.clkr.hw,
718 + },
719 .num_parents = 1,
720 .ops = &clk_branch_ops,
721 .flags = CLK_SET_RATE_PARENT,
722 @@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = {
723 .enable_mask = BIT(11),
724 .hw.init = &(struct clk_init_data){
725 .name = "usb30_utmi_clk",
726 - .parent_names = gcc_pxo_pll8_pll0,
727 + .parent_data = gcc_pxo_pll8_pll0,
728 .num_parents = 3,
729 .ops = &clk_rcg_ops,
730 .flags = CLK_SET_RATE_GATE,
731 @@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_cl
732 .enable_mask = BIT(4),
733 .hw.init = &(struct clk_init_data){
734 .name = "usb30_0_utmi_clk_ctl",
735 - .parent_names = (const char *[]){ "usb30_utmi_clk", },
736 + .parent_hws = (const struct clk_hw*[]){
737 + &usb30_utmi_clk.clkr.hw,
738 + },
739 .num_parents = 1,
740 .ops = &clk_branch_ops,
741 .flags = CLK_SET_RATE_PARENT,
742 @@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_cl
743 .enable_mask = BIT(4),
744 .hw.init = &(struct clk_init_data){
745 .name = "usb30_1_utmi_clk_ctl",
746 - .parent_names = (const char *[]){ "usb30_utmi_clk", },
747 + .parent_hws = (const struct clk_hw*[]){
748 + &usb30_utmi_clk.clkr.hw,
749 + },
750 .num_parents = 1,
751 .ops = &clk_branch_ops,
752 .flags = CLK_SET_RATE_PARENT,
753 @@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
754 .enable_mask = BIT(11),
755 .hw.init = &(struct clk_init_data){
756 .name = "usb_hs1_xcvr_src",
757 - .parent_names = gcc_pxo_pll8_pll0,
758 + .parent_data = gcc_pxo_pll8_pll0,
759 .num_parents = 3,
760 .ops = &clk_rcg_ops,
761 .flags = CLK_SET_RATE_GATE,
762 @@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_cl
763 .enable_mask = BIT(9),
764 .hw.init = &(struct clk_init_data){
765 .name = "usb_hs1_xcvr_clk",
766 - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
767 + .parent_hws = (const struct clk_hw*[]){
768 + &usb_hs1_xcvr_clk_src.clkr.hw,
769 + },
770 .num_parents = 1,
771 .ops = &clk_branch_ops,
772 .flags = CLK_SET_RATE_PARENT,
773 @@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
774 .enable_mask = BIT(11),
775 .hw.init = &(struct clk_init_data){
776 .name = "usb_fs1_xcvr_src",
777 - .parent_names = gcc_pxo_pll8_pll0,
778 + .parent_data = gcc_pxo_pll8_pll0,
779 .num_parents = 3,
780 .ops = &clk_rcg_ops,
781 .flags = CLK_SET_RATE_GATE,
782 @@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_cl
783 .enable_mask = BIT(9),
784 .hw.init = &(struct clk_init_data){
785 .name = "usb_fs1_xcvr_clk",
786 - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
787 + .parent_hws = (const struct clk_hw*[]){
788 + &usb_fs1_xcvr_clk_src.clkr.hw,
789 + },
790 .num_parents = 1,
791 .ops = &clk_branch_ops,
792 .flags = CLK_SET_RATE_PARENT,
793 @@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk
794 .enable_mask = BIT(4),
795 .hw.init = &(struct clk_init_data){
796 .name = "usb_fs1_sys_clk",
797 - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
798 + .parent_hws = (const struct clk_hw*[]){
799 + &usb_fs1_xcvr_clk_src.clkr.hw,
800 + },
801 .num_parents = 1,
802 .ops = &clk_branch_ops,
803 .flags = CLK_SET_RATE_PARENT,
804 @@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src
805 .enable_mask = BIT(1),
806 .hw.init = &(struct clk_init_data){
807 .name = "gmac_core1_src",
808 - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
809 + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
810 .num_parents = 5,
811 .ops = &clk_dyn_rcg_ops,
812 },
813 @@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk
814 .enable_mask = BIT(4),
815 .hw.init = &(struct clk_init_data){
816 .name = "gmac_core1_clk",
817 - .parent_names = (const char *[]){
818 - "gmac_core1_src",
819 + .parent_hws = (const struct clk_hw*[]){
820 + &gmac_core1_src.clkr.hw,
821 },
822 .num_parents = 1,
823 .ops = &clk_branch_ops,
824 @@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src
825 .enable_mask = BIT(1),
826 .hw.init = &(struct clk_init_data){
827 .name = "gmac_core2_src",
828 - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
829 + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
830 .num_parents = 5,
831 .ops = &clk_dyn_rcg_ops,
832 },
833 @@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk
834 .enable_mask = BIT(4),
835 .hw.init = &(struct clk_init_data){
836 .name = "gmac_core2_clk",
837 - .parent_names = (const char *[]){
838 - "gmac_core2_src",
839 + .parent_hws = (const struct clk_hw*[]){
840 + &gmac_core2_src.clkr.hw,
841 },
842 .num_parents = 1,
843 .ops = &clk_branch_ops,
844 @@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src
845 .enable_mask = BIT(1),
846 .hw.init = &(struct clk_init_data){
847 .name = "gmac_core3_src",
848 - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
849 + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
850 .num_parents = 5,
851 .ops = &clk_dyn_rcg_ops,
852 },
853 @@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk
854 .enable_mask = BIT(4),
855 .hw.init = &(struct clk_init_data){
856 .name = "gmac_core3_clk",
857 - .parent_names = (const char *[]){
858 - "gmac_core3_src",
859 + .parent_hws = (const struct clk_hw*[]){
860 + &gmac_core3_src.clkr.hw,
861 },
862 .num_parents = 1,
863 .ops = &clk_branch_ops,
864 @@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src
865 .enable_mask = BIT(1),
866 .hw.init = &(struct clk_init_data){
867 .name = "gmac_core4_src",
868 - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
869 + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
870 .num_parents = 5,
871 .ops = &clk_dyn_rcg_ops,
872 },
873 @@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk
874 .enable_mask = BIT(4),
875 .hw.init = &(struct clk_init_data){
876 .name = "gmac_core4_clk",
877 - .parent_names = (const char *[]){
878 - "gmac_core4_src",
879 + .parent_hws = (const struct clk_hw*[]){
880 + &gmac_core4_src.clkr.hw,
881 },
882 .num_parents = 1,
883 .ops = &clk_branch_ops,
884 @@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src =
885 .enable_mask = BIT(1),
886 .hw.init = &(struct clk_init_data){
887 .name = "nss_tcm_src",
888 - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
889 + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
890 .num_parents = 5,
891 .ops = &clk_dyn_rcg_ops,
892 },
893 @@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = {
894 .enable_mask = BIT(6) | BIT(4),
895 .hw.init = &(struct clk_init_data){
896 .name = "nss_tcm_clk",
897 - .parent_names = (const char *[]){
898 - "nss_tcm_src",
899 + .parent_hws = (const struct clk_hw*[]){
900 + &nss_tcm_src.clkr.hw,
901 },
902 .num_parents = 1,
903 .ops = &clk_branch_ops,
904 @@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_sr
905 .enable_mask = BIT(1),
906 .hw.init = &(struct clk_init_data){
907 .name = "ubi32_core1_src_clk",
908 - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
909 + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
910 .num_parents = 5,
911 .ops = &clk_dyn_rcg_ops,
912 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
913 @@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_sr
914 .enable_mask = BIT(1),
915 .hw.init = &(struct clk_init_data){
916 .name = "ubi32_core2_src_clk",
917 - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
918 + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
919 .num_parents = 5,
920 .ops = &clk_dyn_rcg_ops,
921 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
Staging tree of Stijn Tintel