git.openwrt.org Git - openwrt/staging/dangole.git/blob

   1 From 73b7a6047971aa6ce4a70fc4901964d14f077171 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Wed, 6 Jan 2021 22:32:02 +0100
   4 Subject: [PATCH] net: dsa: bcm_sf2: support BCM4908's integrated switch
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 BCM4908 family SoCs come with integrated Starfighter 2 switch. Its
  10 registers layout it a mix of BCM7278 and BCM7445. It has 5 integrated
  11 PHYs and 8 ports. It also supports RGMII and SerDes.
  12
  13 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  14 Acked-by: Florian Fainelli <f.fainelli@gmail.com>
  15 Link: https://lore.kernel.org/r/20210106213202.17459-3-zajec5@gmail.com
  16 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  17 ---
  18  drivers/net/dsa/b53/b53_common.c | 14 +++++++++++++
  19  drivers/net/dsa/b53/b53_priv.h   |  1 +
  20  drivers/net/dsa/bcm_sf2.c        | 36 +++++++++++++++++++++++++++++---
  21  drivers/net/dsa/bcm_sf2_regs.h   |  1 +
  22  4 files changed, 49 insertions(+), 3 deletions(-)
  23
  24 --- a/drivers/net/dsa/b53/b53_common.c
  25 +++ b/drivers/net/dsa/b53/b53_common.c
  26 @@ -2260,6 +2260,22 @@ static const struct b53_chip_data b53_sw
  27                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
  28                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
  29         },
  30 +       /* Starfighter 2 */
  31 +       {
  32 +               .chip_id = BCM4908_DEVICE_ID,
  33 +               .dev_name = "BCM4908",
  34 +               .vlans = 4096,
  35 +               .enabled_ports = 0x1bf,
  36 +#if 0
  37 +               .arl_bins = 4,
  38 +               .arl_buckets = 256,
  39 +#endif
  40 +               .cpu_port = 8, /* TODO: ports 4, 5, 8 */
  41 +               .vta_regs = B53_VTA_REGS,
  42 +               .duplex_reg = B53_DUPLEX_STAT_GE,
  43 +               .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
  44 +               .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
  45 +       },
  46         {
  47                 .chip_id = BCM7445_DEVICE_ID,
  48                 .dev_name = "BCM7445",
  49 --- a/drivers/net/dsa/b53/b53_priv.h
  50 +++ b/drivers/net/dsa/b53/b53_priv.h
  51 @@ -64,6 +64,7 @@ struct b53_io_ops {
  52  #define B53_INVALID_LANE       0xff
  53
  54  enum {
  55 +       BCM4908_DEVICE_ID = 0x4908,
  56         BCM5325_DEVICE_ID = 0x25,
  57         BCM5365_DEVICE_ID = 0x65,
  58         BCM5389_DEVICE_ID = 0x89,
  59 --- a/drivers/net/dsa/bcm_sf2.c
  60 +++ b/drivers/net/dsa/bcm_sf2.c
  61 @@ -61,7 +61,8 @@ static void bcm_sf2_imp_setup(struct dsa
  62         b53_brcm_hdr_setup(ds, port);
  63
  64         if (port == 8) {
  65 -               if (priv->type == BCM7445_DEVICE_ID)
  66 +               if (priv->type == BCM4908_DEVICE_ID ||
  67 +                   priv->type == BCM7445_DEVICE_ID)
  68                         offset = CORE_STS_OVERRIDE_IMP;
  69                 else
  70                         offset = CORE_STS_OVERRIDE_IMP2;
  71 @@ -542,7 +543,8 @@ static void bcm_sf2_sw_mac_config(struct
  72         if (port == core_readl(priv, CORE_IMP0_PRT_ID))
  73                 return;
  74
  75 -       if (priv->type == BCM7445_DEVICE_ID)
  76 +       if (priv->type == BCM4908_DEVICE_ID ||
  77 +           priv->type == BCM7445_DEVICE_ID)
  78                 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
  79         else
  80                 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
  81 @@ -984,6 +986,30 @@ struct bcm_sf2_of_data {
  82         unsigned int num_cfp_rules;
  83  };
  84
  85 +static const u16 bcm_sf2_4908_reg_offsets[] = {
  86 +       [REG_SWITCH_CNTRL]      = 0x00,
  87 +       [REG_SWITCH_STATUS]     = 0x04,
  88 +       [REG_DIR_DATA_WRITE]    = 0x08,
  89 +       [REG_DIR_DATA_READ]     = 0x0c,
  90 +       [REG_SWITCH_REVISION]   = 0x10,
  91 +       [REG_PHY_REVISION]      = 0x14,
  92 +       [REG_SPHY_CNTRL]        = 0x24,
  93 +       [REG_CROSSBAR]          = 0xc8,
  94 +       [REG_RGMII_0_CNTRL]     = 0xe0,
  95 +       [REG_RGMII_1_CNTRL]     = 0xec,
  96 +       [REG_RGMII_2_CNTRL]     = 0xf8,
  97 +       [REG_LED_0_CNTRL]       = 0x40,
  98 +       [REG_LED_1_CNTRL]       = 0x4c,
  99 +       [REG_LED_2_CNTRL]       = 0x58,
 100 +};
 101 +
 102 +static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
 103 +       .type           = BCM4908_DEVICE_ID,
 104 +       .core_reg_align = 0,
 105 +       .reg_offsets    = bcm_sf2_4908_reg_offsets,
 106 +       .num_cfp_rules  = 0, /* FIXME */
 107 +};
 108 +
 109  /* Register offsets for the SWITCH_REG_* block */
 110  static const u16 bcm_sf2_7445_reg_offsets[] = {
 111         [REG_SWITCH_CNTRL]      = 0x00,
 112 @@ -1032,6 +1058,9 @@ static const struct bcm_sf2_of_data bcm_
 113  };
 114
 115  static const struct of_device_id bcm_sf2_of_match[] = {
 116 +       { .compatible = "brcm,bcm4908-switch",
 117 +         .data = &bcm_sf2_4908_data
 118 +       },
 119         { .compatible = "brcm,bcm7445-switch-v4.0",
 120           .data = &bcm_sf2_7445_data
 121         },
 122 --- a/drivers/net/dsa/bcm_sf2_regs.h
 123 +++ b/drivers/net/dsa/bcm_sf2_regs.h
 124 @@ -17,6 +17,7 @@ enum bcm_sf2_reg_offs {
 125         REG_SWITCH_REVISION,
 126         REG_PHY_REVISION,
 127         REG_SPHY_CNTRL,
 128 +       REG_CROSSBAR,
 129         REG_RGMII_0_CNTRL,
 130         REG_RGMII_1_CNTRL,
 131         REG_RGMII_2_CNTRL,