git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From ae5d39403c61f4ed691a0a8d94673210475242be Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Tue, 15 Aug 2017 16:47:18 -0700
   4 Subject: [PATCH 204/454] drm/vc4: Move the DSI clock divider workaround closer
   5  to the clock call.
   6
   7 We want the adjusted_mode->clock to be the actual clock we're
   8 expecting to program, so that consumers see the right values for clock
   9 and vrefresh.
  10
  11 Signed-off-by: Eric Anholt <eric@anholt.net>
  12 Link: https://patchwork.freedesktop.org/patch/msgid/20170815234722.20700-1-eric@anholt.net
  13 Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  14 (cherry picked from commit d409eeafa9ba1c0f2eb75a2619fc787808a545e4)
  15 ---
  16  drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------
  17  1 file changed, 6 insertions(+), 6 deletions(-)
  18
  19 --- a/drivers/gpu/drm/vc4/vc4_dsi.c
  20 +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
  21 @@ -864,11 +864,7 @@ static bool vc4_dsi_encoder_mode_fixup(s
  22         pll_clock = parent_rate / divider;
  23         pixel_clock_hz = pll_clock / dsi->divider;
  24
  25 -       /* Round up the clk_set_rate() request slightly, since
  26 -        * PLLD_DSI1 is an integer divider and its rate selection will
  27 -        * never round up.
  28 -        */
  29 -       adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
  30 +       adjusted_mode->clock = pixel_clock_hz / 1000;
  31
  32         /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
  33         adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
  34 @@ -906,7 +902,11 @@ static void vc4_dsi_encoder_enable(struc
  35                 vc4_dsi_dump_regs(dsi);
  36         }
  37
  38 -       phy_clock = pixel_clock_hz * dsi->divider;
  39 +       /* Round up the clk_set_rate() request slightly, since
  40 +        * PLLD_DSI1 is an integer divider and its rate selection will
  41 +        * never round up.
  42 +        */
  43 +       phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
  44         ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
  45         if (ret) {
  46                 dev_err(&dsi->pdev->dev,