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1 From 5e3aac197a74914ccec2732a89c29d960730d28f Mon Sep 17 00:00:00 2001
2 From: Balsam CHIHI <bchihi@baylibre.com>
3 Date: Thu, 9 Feb 2023 11:56:23 +0100
4 Subject: [PATCH 05/42] thermal/drivers/mediatek: Relocate driver to mediatek
5 folder
6
7 Add MediaTek proprietary folder to upstream more thermal zone and cooler
8 drivers, relocate the original thermal controller driver to it, and rename it
9 as "auxadc_thermal.c" to show its purpose more clearly.
10
11 Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
12 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
13 Link: https://lore.kernel.org/r/20230209105628.50294-2-bchihi@baylibre.com
14 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
15 Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
16 ---
17 drivers/thermal/Kconfig | 14 ++++---------
18 drivers/thermal/Makefile | 2 +-
19 drivers/thermal/mediatek/Kconfig | 21 +++++++++++++++++++
20 drivers/thermal/mediatek/Makefile | 1 +
21 .../auxadc_thermal.c} | 2 +-
22 5 files changed, 28 insertions(+), 12 deletions(-)
23 create mode 100644 drivers/thermal/mediatek/Kconfig
24 create mode 100644 drivers/thermal/mediatek/Makefile
25 rename drivers/thermal/{mtk_thermal.c => mediatek/auxadc_thermal.c} (99%)
26
27 --- a/drivers/thermal/Kconfig
28 +++ b/drivers/thermal/Kconfig
29 @@ -412,16 +412,10 @@ config DA9062_THERMAL
30 zone.
31 Compatible with the DA9062 and DA9061 PMICs.
32
33 -config MTK_THERMAL
34 - tristate "Temperature sensor driver for mediatek SoCs"
35 - depends on ARCH_MEDIATEK || COMPILE_TEST
36 - depends on HAS_IOMEM
37 - depends on NVMEM || NVMEM=n
38 - depends on RESET_CONTROLLER
39 - default y
40 - help
41 - Enable this option if you want to have support for thermal management
42 - controller present in Mediatek SoCs
43 +menu "Mediatek thermal drivers"
44 +depends on ARCH_MEDIATEK || COMPILE_TEST
45 +source "drivers/thermal/mediatek/Kconfig"
46 +endmenu
47
48 config AMLOGIC_THERMAL
49 tristate "Amlogic Thermal Support"
50 --- a/drivers/thermal/Makefile
51 +++ b/drivers/thermal/Makefile
52 @@ -55,7 +55,7 @@ obj-y += st/
53 obj-y += qcom/
54 obj-y += tegra/
55 obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
56 -obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
57 +obj-y += mediatek/
58 obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
59 obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o
60 obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o
61 --- /dev/null
62 +++ b/drivers/thermal/mediatek/Kconfig
63 @@ -0,0 +1,21 @@
64 +config MTK_THERMAL
65 + tristate "MediaTek thermal drivers"
66 + depends on THERMAL_OF
67 + help
68 + This is the option for MediaTek thermal software solutions.
69 + Please enable corresponding options to get temperature
70 + information from thermal sensors or turn on throttle
71 + mechaisms for thermal mitigation.
72 +
73 +if MTK_THERMAL
74 +
75 +config MTK_SOC_THERMAL
76 + tristate "AUXADC temperature sensor driver for MediaTek SoCs"
77 + depends on HAS_IOMEM
78 + help
79 + Enable this option if you want to get SoC temperature
80 + information for MediaTek platforms.
81 + This driver configures thermal controllers to collect
82 + temperature via AUXADC interface.
83 +
84 +endif
85 --- /dev/null
86 +++ b/drivers/thermal/mediatek/Makefile
87 @@ -0,0 +1 @@
88 +obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o
89 --- a/drivers/thermal/mtk_thermal.c
90 +++ /dev/null
91 @@ -1,1254 +0,0 @@
92 -// SPDX-License-Identifier: GPL-2.0-only
93 -/*
94 - * Copyright (c) 2015 MediaTek Inc.
95 - * Author: Hanyi Wu <hanyi.wu@mediatek.com>
96 - * Sascha Hauer <s.hauer@pengutronix.de>
97 - * Dawei Chien <dawei.chien@mediatek.com>
98 - * Louis Yu <louis.yu@mediatek.com>
99 - */
100 -
101 -#include <linux/clk.h>
102 -#include <linux/delay.h>
103 -#include <linux/interrupt.h>
104 -#include <linux/kernel.h>
105 -#include <linux/module.h>
106 -#include <linux/nvmem-consumer.h>
107 -#include <linux/of.h>
108 -#include <linux/of_address.h>
109 -#include <linux/of_device.h>
110 -#include <linux/platform_device.h>
111 -#include <linux/slab.h>
112 -#include <linux/io.h>
113 -#include <linux/thermal.h>
114 -#include <linux/reset.h>
115 -#include <linux/types.h>
116 -
117 -#include "thermal_hwmon.h"
118 -
119 -/* AUXADC Registers */
120 -#define AUXADC_CON1_SET_V 0x008
121 -#define AUXADC_CON1_CLR_V 0x00c
122 -#define AUXADC_CON2_V 0x010
123 -#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
124 -
125 -#define APMIXED_SYS_TS_CON1 0x604
126 -
127 -/* Thermal Controller Registers */
128 -#define TEMP_MONCTL0 0x000
129 -#define TEMP_MONCTL1 0x004
130 -#define TEMP_MONCTL2 0x008
131 -#define TEMP_MONIDET0 0x014
132 -#define TEMP_MONIDET1 0x018
133 -#define TEMP_MSRCTL0 0x038
134 -#define TEMP_MSRCTL1 0x03c
135 -#define TEMP_AHBPOLL 0x040
136 -#define TEMP_AHBTO 0x044
137 -#define TEMP_ADCPNP0 0x048
138 -#define TEMP_ADCPNP1 0x04c
139 -#define TEMP_ADCPNP2 0x050
140 -#define TEMP_ADCPNP3 0x0b4
141 -
142 -#define TEMP_ADCMUX 0x054
143 -#define TEMP_ADCEN 0x060
144 -#define TEMP_PNPMUXADDR 0x064
145 -#define TEMP_ADCMUXADDR 0x068
146 -#define TEMP_ADCENADDR 0x074
147 -#define TEMP_ADCVALIDADDR 0x078
148 -#define TEMP_ADCVOLTADDR 0x07c
149 -#define TEMP_RDCTRL 0x080
150 -#define TEMP_ADCVALIDMASK 0x084
151 -#define TEMP_ADCVOLTAGESHIFT 0x088
152 -#define TEMP_ADCWRITECTRL 0x08c
153 -#define TEMP_MSR0 0x090
154 -#define TEMP_MSR1 0x094
155 -#define TEMP_MSR2 0x098
156 -#define TEMP_MSR3 0x0B8
157 -
158 -#define TEMP_SPARE0 0x0f0
159 -
160 -#define TEMP_ADCPNP0_1 0x148
161 -#define TEMP_ADCPNP1_1 0x14c
162 -#define TEMP_ADCPNP2_1 0x150
163 -#define TEMP_MSR0_1 0x190
164 -#define TEMP_MSR1_1 0x194
165 -#define TEMP_MSR2_1 0x198
166 -#define TEMP_ADCPNP3_1 0x1b4
167 -#define TEMP_MSR3_1 0x1B8
168 -
169 -#define PTPCORESEL 0x400
170 -
171 -#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
172 -
173 -#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
174 -#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
175 -
176 -#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
177 -
178 -#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
179 -#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
180 -
181 -#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
182 -#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
183 -
184 -/* MT8173 thermal sensors */
185 -#define MT8173_TS1 0
186 -#define MT8173_TS2 1
187 -#define MT8173_TS3 2
188 -#define MT8173_TS4 3
189 -#define MT8173_TSABB 4
190 -
191 -/* AUXADC channel 11 is used for the temperature sensors */
192 -#define MT8173_TEMP_AUXADC_CHANNEL 11
193 -
194 -/* The total number of temperature sensors in the MT8173 */
195 -#define MT8173_NUM_SENSORS 5
196 -
197 -/* The number of banks in the MT8173 */
198 -#define MT8173_NUM_ZONES 4
199 -
200 -/* The number of sensing points per bank */
201 -#define MT8173_NUM_SENSORS_PER_ZONE 4
202 -
203 -/* The number of controller in the MT8173 */
204 -#define MT8173_NUM_CONTROLLER 1
205 -
206 -/* The calibration coefficient of sensor */
207 -#define MT8173_CALIBRATION 165
208 -
209 -/*
210 - * Layout of the fuses providing the calibration data
211 - * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
212 - * MT8183 has 6 sensors and needs 6 VTS calibration data.
213 - * MT8173 has 5 sensors and needs 5 VTS calibration data.
214 - * MT2701 has 3 sensors and needs 3 VTS calibration data.
215 - * MT2712 has 4 sensors and needs 4 VTS calibration data.
216 - */
217 -#define CALIB_BUF0_VALID_V1 BIT(0)
218 -#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
219 -#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
220 -#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
221 -#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
222 -#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
223 -#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
224 -#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
225 -#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
226 -#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
227 -#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
228 -#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
229 -
230 -/*
231 - * Layout of the fuses providing the calibration data
232 - * These macros could be used for MT7622.
233 - */
234 -#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
235 -#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
236 -#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
237 -#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
238 -#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
239 -#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
240 -#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
241 -#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
242 -#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
243 -
244 -/*
245 - * Layout of the fuses providing the calibration data
246 - * These macros can be used for MT7981 and MT7986.
247 - */
248 -#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
249 -#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
250 -#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
251 -#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
252 -#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
253 -#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
254 -#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
255 -#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
256 -#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
257 -
258 -enum {
259 - VTS1,
260 - VTS2,
261 - VTS3,
262 - VTS4,
263 - VTS5,
264 - VTSABB,
265 - MAX_NUM_VTS,
266 -};
267 -
268 -enum mtk_thermal_version {
269 - MTK_THERMAL_V1 = 1,
270 - MTK_THERMAL_V2,
271 - MTK_THERMAL_V3,
272 -};
273 -
274 -/* MT2701 thermal sensors */
275 -#define MT2701_TS1 0
276 -#define MT2701_TS2 1
277 -#define MT2701_TSABB 2
278 -
279 -/* AUXADC channel 11 is used for the temperature sensors */
280 -#define MT2701_TEMP_AUXADC_CHANNEL 11
281 -
282 -/* The total number of temperature sensors in the MT2701 */
283 -#define MT2701_NUM_SENSORS 3
284 -
285 -/* The number of sensing points per bank */
286 -#define MT2701_NUM_SENSORS_PER_ZONE 3
287 -
288 -/* The number of controller in the MT2701 */
289 -#define MT2701_NUM_CONTROLLER 1
290 -
291 -/* The calibration coefficient of sensor */
292 -#define MT2701_CALIBRATION 165
293 -
294 -/* MT2712 thermal sensors */
295 -#define MT2712_TS1 0
296 -#define MT2712_TS2 1
297 -#define MT2712_TS3 2
298 -#define MT2712_TS4 3
299 -
300 -/* AUXADC channel 11 is used for the temperature sensors */
301 -#define MT2712_TEMP_AUXADC_CHANNEL 11
302 -
303 -/* The total number of temperature sensors in the MT2712 */
304 -#define MT2712_NUM_SENSORS 4
305 -
306 -/* The number of sensing points per bank */
307 -#define MT2712_NUM_SENSORS_PER_ZONE 4
308 -
309 -/* The number of controller in the MT2712 */
310 -#define MT2712_NUM_CONTROLLER 1
311 -
312 -/* The calibration coefficient of sensor */
313 -#define MT2712_CALIBRATION 165
314 -
315 -#define MT7622_TEMP_AUXADC_CHANNEL 11
316 -#define MT7622_NUM_SENSORS 1
317 -#define MT7622_NUM_ZONES 1
318 -#define MT7622_NUM_SENSORS_PER_ZONE 1
319 -#define MT7622_TS1 0
320 -#define MT7622_NUM_CONTROLLER 1
321 -
322 -/* The maximum number of banks */
323 -#define MAX_NUM_ZONES 8
324 -
325 -/* The calibration coefficient of sensor */
326 -#define MT7622_CALIBRATION 165
327 -
328 -/* MT8183 thermal sensors */
329 -#define MT8183_TS1 0
330 -#define MT8183_TS2 1
331 -#define MT8183_TS3 2
332 -#define MT8183_TS4 3
333 -#define MT8183_TS5 4
334 -#define MT8183_TSABB 5
335 -
336 -/* AUXADC channel is used for the temperature sensors */
337 -#define MT8183_TEMP_AUXADC_CHANNEL 11
338 -
339 -/* The total number of temperature sensors in the MT8183 */
340 -#define MT8183_NUM_SENSORS 6
341 -
342 -/* The number of banks in the MT8183 */
343 -#define MT8183_NUM_ZONES 1
344 -
345 -/* The number of sensing points per bank */
346 -#define MT8183_NUM_SENSORS_PER_ZONE 6
347 -
348 -/* The number of controller in the MT8183 */
349 -#define MT8183_NUM_CONTROLLER 2
350 -
351 -/* The calibration coefficient of sensor */
352 -#define MT8183_CALIBRATION 153
353 -
354 -/* AUXADC channel 11 is used for the temperature sensors */
355 -#define MT7986_TEMP_AUXADC_CHANNEL 11
356 -
357 -/* The total number of temperature sensors in the MT7986 */
358 -#define MT7986_NUM_SENSORS 1
359 -
360 -/* The number of banks in the MT7986 */
361 -#define MT7986_NUM_ZONES 1
362 -
363 -/* The number of sensing points per bank */
364 -#define MT7986_NUM_SENSORS_PER_ZONE 1
365 -
366 -/* MT7986 thermal sensors */
367 -#define MT7986_TS1 0
368 -
369 -/* The number of controller in the MT7986 */
370 -#define MT7986_NUM_CONTROLLER 1
371 -
372 -/* The calibration coefficient of sensor */
373 -#define MT7986_CALIBRATION 165
374 -
375 -struct mtk_thermal;
376 -
377 -struct thermal_bank_cfg {
378 - unsigned int num_sensors;
379 - const int *sensors;
380 -};
381 -
382 -struct mtk_thermal_bank {
383 - struct mtk_thermal *mt;
384 - int id;
385 -};
386 -
387 -struct mtk_thermal_data {
388 - s32 num_banks;
389 - s32 num_sensors;
390 - s32 auxadc_channel;
391 - const int *vts_index;
392 - const int *sensor_mux_values;
393 - const int *msr;
394 - const int *adcpnp;
395 - const int cali_val;
396 - const int num_controller;
397 - const int *controller_offset;
398 - bool need_switch_bank;
399 - struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
400 - enum mtk_thermal_version version;
401 -};
402 -
403 -struct mtk_thermal {
404 - struct device *dev;
405 - void __iomem *thermal_base;
406 -
407 - struct clk *clk_peri_therm;
408 - struct clk *clk_auxadc;
409 - /* lock: for getting and putting banks */
410 - struct mutex lock;
411 -
412 - /* Calibration values */
413 - s32 adc_ge;
414 - s32 adc_oe;
415 - s32 degc_cali;
416 - s32 o_slope;
417 - s32 o_slope_sign;
418 - s32 vts[MAX_NUM_VTS];
419 -
420 - const struct mtk_thermal_data *conf;
421 - struct mtk_thermal_bank banks[MAX_NUM_ZONES];
422 -
423 - int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
424 -};
425 -
426 -/* MT8183 thermal sensor data */
427 -static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
428 - MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
429 -};
430 -
431 -static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
432 - TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
433 -};
434 -
435 -static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
436 - TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
437 - TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
438 -};
439 -
440 -static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
441 -static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
442 -
443 -static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
444 - VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
445 -};
446 -
447 -/* MT8173 thermal sensor data */
448 -static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
449 - { MT8173_TS2, MT8173_TS3 },
450 - { MT8173_TS2, MT8173_TS4 },
451 - { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
452 - { MT8173_TS2 },
453 -};
454 -
455 -static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
456 - TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
457 -};
458 -
459 -static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
460 - TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
461 -};
462 -
463 -static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
464 -static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
465 -
466 -static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
467 - VTS1, VTS2, VTS3, VTS4, VTSABB
468 -};
469 -
470 -/* MT2701 thermal sensor data */
471 -static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
472 - MT2701_TS1, MT2701_TS2, MT2701_TSABB
473 -};
474 -
475 -static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
476 - TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
477 -};
478 -
479 -static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
480 - TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
481 -};
482 -
483 -static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
484 -static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
485 -
486 -static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
487 - VTS1, VTS2, VTS3
488 -};
489 -
490 -/* MT2712 thermal sensor data */
491 -static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
492 - MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
493 -};
494 -
495 -static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
496 - TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
497 -};
498 -
499 -static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
500 - TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
501 -};
502 -
503 -static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
504 -static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
505 -
506 -static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
507 - VTS1, VTS2, VTS3, VTS4
508 -};
509 -
510 -/* MT7622 thermal sensor data */
511 -static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
512 -static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
513 -static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
514 -static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
515 -static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
516 -static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
517 -
518 -/* MT7986 thermal sensor data */
519 -static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
520 -static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
521 -static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
522 -static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
523 -static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
524 -static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
525 -
526 -/*
527 - * The MT8173 thermal controller has four banks. Each bank can read up to
528 - * four temperature sensors simultaneously. The MT8173 has a total of 5
529 - * temperature sensors. We use each bank to measure a certain area of the
530 - * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
531 - * areas, hence is used in different banks.
532 - *
533 - * The thermal core only gets the maximum temperature of all banks, so
534 - * the bank concept wouldn't be necessary here. However, the SVS (Smart
535 - * Voltage Scaling) unit makes its decisions based on the same bank
536 - * data, and this indeed needs the temperatures of the individual banks
537 - * for making better decisions.
538 - */
539 -static const struct mtk_thermal_data mt8173_thermal_data = {
540 - .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
541 - .num_banks = MT8173_NUM_ZONES,
542 - .num_sensors = MT8173_NUM_SENSORS,
543 - .vts_index = mt8173_vts_index,
544 - .cali_val = MT8173_CALIBRATION,
545 - .num_controller = MT8173_NUM_CONTROLLER,
546 - .controller_offset = mt8173_tc_offset,
547 - .need_switch_bank = true,
548 - .bank_data = {
549 - {
550 - .num_sensors = 2,
551 - .sensors = mt8173_bank_data[0],
552 - }, {
553 - .num_sensors = 2,
554 - .sensors = mt8173_bank_data[1],
555 - }, {
556 - .num_sensors = 3,
557 - .sensors = mt8173_bank_data[2],
558 - }, {
559 - .num_sensors = 1,
560 - .sensors = mt8173_bank_data[3],
561 - },
562 - },
563 - .msr = mt8173_msr,
564 - .adcpnp = mt8173_adcpnp,
565 - .sensor_mux_values = mt8173_mux_values,
566 - .version = MTK_THERMAL_V1,
567 -};
568 -
569 -/*
570 - * The MT2701 thermal controller has one bank, which can read up to
571 - * three temperature sensors simultaneously. The MT2701 has a total of 3
572 - * temperature sensors.
573 - *
574 - * The thermal core only gets the maximum temperature of this one bank,
575 - * so the bank concept wouldn't be necessary here. However, the SVS (Smart
576 - * Voltage Scaling) unit makes its decisions based on the same bank
577 - * data.
578 - */
579 -static const struct mtk_thermal_data mt2701_thermal_data = {
580 - .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
581 - .num_banks = 1,
582 - .num_sensors = MT2701_NUM_SENSORS,
583 - .vts_index = mt2701_vts_index,
584 - .cali_val = MT2701_CALIBRATION,
585 - .num_controller = MT2701_NUM_CONTROLLER,
586 - .controller_offset = mt2701_tc_offset,
587 - .need_switch_bank = true,
588 - .bank_data = {
589 - {
590 - .num_sensors = 3,
591 - .sensors = mt2701_bank_data,
592 - },
593 - },
594 - .msr = mt2701_msr,
595 - .adcpnp = mt2701_adcpnp,
596 - .sensor_mux_values = mt2701_mux_values,
597 - .version = MTK_THERMAL_V1,
598 -};
599 -
600 -/*
601 - * The MT2712 thermal controller has one bank, which can read up to
602 - * four temperature sensors simultaneously. The MT2712 has a total of 4
603 - * temperature sensors.
604 - *
605 - * The thermal core only gets the maximum temperature of this one bank,
606 - * so the bank concept wouldn't be necessary here. However, the SVS (Smart
607 - * Voltage Scaling) unit makes its decisions based on the same bank
608 - * data.
609 - */
610 -static const struct mtk_thermal_data mt2712_thermal_data = {
611 - .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
612 - .num_banks = 1,
613 - .num_sensors = MT2712_NUM_SENSORS,
614 - .vts_index = mt2712_vts_index,
615 - .cali_val = MT2712_CALIBRATION,
616 - .num_controller = MT2712_NUM_CONTROLLER,
617 - .controller_offset = mt2712_tc_offset,
618 - .need_switch_bank = true,
619 - .bank_data = {
620 - {
621 - .num_sensors = 4,
622 - .sensors = mt2712_bank_data,
623 - },
624 - },
625 - .msr = mt2712_msr,
626 - .adcpnp = mt2712_adcpnp,
627 - .sensor_mux_values = mt2712_mux_values,
628 - .version = MTK_THERMAL_V1,
629 -};
630 -
631 -/*
632 - * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
633 - * access.
634 - */
635 -static const struct mtk_thermal_data mt7622_thermal_data = {
636 - .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
637 - .num_banks = MT7622_NUM_ZONES,
638 - .num_sensors = MT7622_NUM_SENSORS,
639 - .vts_index = mt7622_vts_index,
640 - .cali_val = MT7622_CALIBRATION,
641 - .num_controller = MT7622_NUM_CONTROLLER,
642 - .controller_offset = mt7622_tc_offset,
643 - .need_switch_bank = true,
644 - .bank_data = {
645 - {
646 - .num_sensors = 1,
647 - .sensors = mt7622_bank_data,
648 - },
649 - },
650 - .msr = mt7622_msr,
651 - .adcpnp = mt7622_adcpnp,
652 - .sensor_mux_values = mt7622_mux_values,
653 - .version = MTK_THERMAL_V2,
654 -};
655 -
656 -/*
657 - * The MT8183 thermal controller has one bank for the current SW framework.
658 - * The MT8183 has a total of 6 temperature sensors.
659 - * There are two thermal controller to control the six sensor.
660 - * The first one bind 2 sensor, and the other bind 4 sensors.
661 - * The thermal core only gets the maximum temperature of all sensor, so
662 - * the bank concept wouldn't be necessary here. However, the SVS (Smart
663 - * Voltage Scaling) unit makes its decisions based on the same bank
664 - * data, and this indeed needs the temperatures of the individual banks
665 - * for making better decisions.
666 - */
667 -static const struct mtk_thermal_data mt8183_thermal_data = {
668 - .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
669 - .num_banks = MT8183_NUM_ZONES,
670 - .num_sensors = MT8183_NUM_SENSORS,
671 - .vts_index = mt8183_vts_index,
672 - .cali_val = MT8183_CALIBRATION,
673 - .num_controller = MT8183_NUM_CONTROLLER,
674 - .controller_offset = mt8183_tc_offset,
675 - .need_switch_bank = false,
676 - .bank_data = {
677 - {
678 - .num_sensors = 6,
679 - .sensors = mt8183_bank_data,
680 - },
681 - },
682 -
683 - .msr = mt8183_msr,
684 - .adcpnp = mt8183_adcpnp,
685 - .sensor_mux_values = mt8183_mux_values,
686 - .version = MTK_THERMAL_V1,
687 -};
688 -
689 -/*
690 - * MT7986 uses AUXADC Channel 11 for raw data access.
691 - */
692 -static const struct mtk_thermal_data mt7986_thermal_data = {
693 - .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
694 - .num_banks = MT7986_NUM_ZONES,
695 - .num_sensors = MT7986_NUM_SENSORS,
696 - .vts_index = mt7986_vts_index,
697 - .cali_val = MT7986_CALIBRATION,
698 - .num_controller = MT7986_NUM_CONTROLLER,
699 - .controller_offset = mt7986_tc_offset,
700 - .need_switch_bank = true,
701 - .bank_data = {
702 - {
703 - .num_sensors = 1,
704 - .sensors = mt7986_bank_data,
705 - },
706 - },
707 - .msr = mt7986_msr,
708 - .adcpnp = mt7986_adcpnp,
709 - .sensor_mux_values = mt7986_mux_values,
710 - .version = MTK_THERMAL_V3,
711 -};
712 -
713 -/**
714 - * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
715 - * @mt: The thermal controller
716 - * @sensno: sensor number
717 - * @raw: raw ADC value
718 - *
719 - * This converts the raw ADC value to mcelsius using the SoC specific
720 - * calibration constants
721 - */
722 -static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
723 -{
724 - s32 tmp;
725 -
726 - raw &= 0xfff;
727 -
728 - tmp = 203450520 << 3;
729 - tmp /= mt->conf->cali_val + mt->o_slope;
730 - tmp /= 10000 + mt->adc_ge;
731 - tmp *= raw - mt->vts[sensno] - 3350;
732 - tmp >>= 3;
733 -
734 - return mt->degc_cali * 500 - tmp;
735 -}
736 -
737 -static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
738 -{
739 - s32 format_1;
740 - s32 format_2;
741 - s32 g_oe;
742 - s32 g_gain;
743 - s32 g_x_roomt;
744 - s32 tmp;
745 -
746 - if (raw == 0)
747 - return 0;
748 -
749 - raw &= 0xfff;
750 - g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
751 - g_oe = mt->adc_oe - 512;
752 - format_1 = mt->vts[VTS2] + 3105 - g_oe;
753 - format_2 = (mt->degc_cali * 10) >> 1;
754 - g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
755 -
756 - tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
757 - tmp = tmp * 10 * 100 / 11;
758 -
759 - if (mt->o_slope_sign == 0)
760 - tmp = tmp / (165 - mt->o_slope);
761 - else
762 - tmp = tmp / (165 + mt->o_slope);
763 -
764 - return (format_2 - tmp) * 100;
765 -}
766 -
767 -static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
768 -{
769 - s32 tmp;
770 -
771 - if (raw == 0)
772 - return 0;
773 -
774 - raw &= 0xfff;
775 - tmp = 100000 * 15 / 16 * 10000;
776 - tmp /= 4096 - 512 + mt->adc_ge;
777 - tmp /= 1490;
778 - tmp *= raw - mt->vts[sensno] - 2900;
779 -
780 - return mt->degc_cali * 500 - tmp;
781 -}
782 -
783 -/**
784 - * mtk_thermal_get_bank - get bank
785 - * @bank: The bank
786 - *
787 - * The bank registers are banked, we have to select a bank in the
788 - * PTPCORESEL register to access it.
789 - */
790 -static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
791 -{
792 - struct mtk_thermal *mt = bank->mt;
793 - u32 val;
794 -
795 - if (mt->conf->need_switch_bank) {
796 - mutex_lock(&mt->lock);
797 -
798 - val = readl(mt->thermal_base + PTPCORESEL);
799 - val &= ~0xf;
800 - val |= bank->id;
801 - writel(val, mt->thermal_base + PTPCORESEL);
802 - }
803 -}
804 -
805 -/**
806 - * mtk_thermal_put_bank - release bank
807 - * @bank: The bank
808 - *
809 - * release a bank previously taken with mtk_thermal_get_bank,
810 - */
811 -static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
812 -{
813 - struct mtk_thermal *mt = bank->mt;
814 -
815 - if (mt->conf->need_switch_bank)
816 - mutex_unlock(&mt->lock);
817 -}
818 -
819 -/**
820 - * mtk_thermal_bank_temperature - get the temperature of a bank
821 - * @bank: The bank
822 - *
823 - * The temperature of a bank is considered the maximum temperature of
824 - * the sensors associated to the bank.
825 - */
826 -static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
827 -{
828 - struct mtk_thermal *mt = bank->mt;
829 - const struct mtk_thermal_data *conf = mt->conf;
830 - int i, temp = INT_MIN, max = INT_MIN;
831 - u32 raw;
832 -
833 - for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
834 - raw = readl(mt->thermal_base + conf->msr[i]);
835 -
836 - temp = mt->raw_to_mcelsius(
837 - mt, conf->bank_data[bank->id].sensors[i], raw);
838 -
839 -
840 - /*
841 - * The first read of a sensor often contains very high bogus
842 - * temperature value. Filter these out so that the system does
843 - * not immediately shut down.
844 - */
845 - if (temp > 200000)
846 - temp = 0;
847 -
848 - if (temp > max)
849 - max = temp;
850 - }
851 -
852 - return max;
853 -}
854 -
855 -static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
856 -{
857 - struct mtk_thermal *mt = tz->devdata;
858 - int i;
859 - int tempmax = INT_MIN;
860 -
861 - for (i = 0; i < mt->conf->num_banks; i++) {
862 - struct mtk_thermal_bank *bank = &mt->banks[i];
863 -
864 - mtk_thermal_get_bank(bank);
865 -
866 - tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
867 -
868 - mtk_thermal_put_bank(bank);
869 - }
870 -
871 - *temperature = tempmax;
872 -
873 - return 0;
874 -}
875 -
876 -static const struct thermal_zone_device_ops mtk_thermal_ops = {
877 - .get_temp = mtk_read_temp,
878 -};
879 -
880 -static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
881 - u32 apmixed_phys_base, u32 auxadc_phys_base,
882 - int ctrl_id)
883 -{
884 - struct mtk_thermal_bank *bank = &mt->banks[num];
885 - const struct mtk_thermal_data *conf = mt->conf;
886 - int i;
887 -
888 - int offset = mt->conf->controller_offset[ctrl_id];
889 - void __iomem *controller_base = mt->thermal_base + offset;
890 -
891 - bank->id = num;
892 - bank->mt = mt;
893 -
894 - mtk_thermal_get_bank(bank);
895 -
896 - /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
897 - writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
898 -
899 - /*
900 - * filt interval is 1 * 46.540us = 46.54us,
901 - * sen interval is 429 * 46.540us = 19.96ms
902 - */
903 - writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
904 - TEMP_MONCTL2_SENSOR_INTERVAL(429),
905 - controller_base + TEMP_MONCTL2);
906 -
907 - /* poll is set to 10u */
908 - writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
909 - controller_base + TEMP_AHBPOLL);
910 -
911 - /* temperature sampling control, 1 sample */
912 - writel(0x0, controller_base + TEMP_MSRCTL0);
913 -
914 - /* exceed this polling time, IRQ would be inserted */
915 - writel(0xffffffff, controller_base + TEMP_AHBTO);
916 -
917 - /* number of interrupts per event, 1 is enough */
918 - writel(0x0, controller_base + TEMP_MONIDET0);
919 - writel(0x0, controller_base + TEMP_MONIDET1);
920 -
921 - /*
922 - * The MT8173 thermal controller does not have its own ADC. Instead it
923 - * uses AHB bus accesses to control the AUXADC. To do this the thermal
924 - * controller has to be programmed with the physical addresses of the
925 - * AUXADC registers and with the various bit positions in the AUXADC.
926 - * Also the thermal controller controls a mux in the APMIXEDSYS register
927 - * space.
928 - */
929 -
930 - /*
931 - * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
932 - * automatically by hw
933 - */
934 - writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
935 -
936 - /* AHB address for auxadc mux selection */
937 - writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
938 - controller_base + TEMP_ADCMUXADDR);
939 -
940 - if (mt->conf->version == MTK_THERMAL_V1) {
941 - /* AHB address for pnp sensor mux selection */
942 - writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
943 - controller_base + TEMP_PNPMUXADDR);
944 - }
945 -
946 - /* AHB value for auxadc enable */
947 - writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
948 -
949 - /* AHB address for auxadc enable (channel 0 immediate mode selected) */
950 - writel(auxadc_phys_base + AUXADC_CON1_SET_V,
951 - controller_base + TEMP_ADCENADDR);
952 -
953 - /* AHB address for auxadc valid bit */
954 - writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
955 - controller_base + TEMP_ADCVALIDADDR);
956 -
957 - /* AHB address for auxadc voltage output */
958 - writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
959 - controller_base + TEMP_ADCVOLTADDR);
960 -
961 - /* read valid & voltage are at the same register */
962 - writel(0x0, controller_base + TEMP_RDCTRL);
963 -
964 - /* indicate where the valid bit is */
965 - writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
966 - controller_base + TEMP_ADCVALIDMASK);
967 -
968 - /* no shift */
969 - writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
970 -
971 - /* enable auxadc mux write transaction */
972 - writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
973 - controller_base + TEMP_ADCWRITECTRL);
974 -
975 - for (i = 0; i < conf->bank_data[num].num_sensors; i++)
976 - writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
977 - mt->thermal_base + conf->adcpnp[i]);
978 -
979 - writel((1 << conf->bank_data[num].num_sensors) - 1,
980 - controller_base + TEMP_MONCTL0);
981 -
982 - writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
983 - TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
984 - controller_base + TEMP_ADCWRITECTRL);
985 -
986 - mtk_thermal_put_bank(bank);
987 -}
988 -
989 -static u64 of_get_phys_base(struct device_node *np)
990 -{
991 - u64 size64;
992 - const __be32 *regaddr_p;
993 -
994 - regaddr_p = of_get_address(np, 0, &size64, NULL);
995 - if (!regaddr_p)
996 - return OF_BAD_ADDR;
997 -
998 - return of_translate_address(np, regaddr_p);
999 -}
1000 -
1001 -static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
1002 -{
1003 - int i;
1004 -
1005 - if (!(buf[0] & CALIB_BUF0_VALID_V1))
1006 - return -EINVAL;
1007 -
1008 - mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
1009 -
1010 - for (i = 0; i < mt->conf->num_sensors; i++) {
1011 - switch (mt->conf->vts_index[i]) {
1012 - case VTS1:
1013 - mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
1014 - break;
1015 - case VTS2:
1016 - mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
1017 - break;
1018 - case VTS3:
1019 - mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
1020 - break;
1021 - case VTS4:
1022 - mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
1023 - break;
1024 - case VTS5:
1025 - mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
1026 - break;
1027 - case VTSABB:
1028 - mt->vts[VTSABB] =
1029 - CALIB_BUF2_VTS_TSABB_V1(buf[2]);
1030 - break;
1031 - default:
1032 - break;
1033 - }
1034 - }
1035 -
1036 - mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
1037 - if (CALIB_BUF1_ID_V1(buf[1]) &
1038 - CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
1039 - mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
1040 - else
1041 - mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
1042 -
1043 - return 0;
1044 -}
1045 -
1046 -static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
1047 -{
1048 - if (!CALIB_BUF1_VALID_V2(buf[1]))
1049 - return -EINVAL;
1050 -
1051 - mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
1052 - mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
1053 - mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
1054 - mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
1055 - mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
1056 - mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
1057 - mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
1058 - mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
1059 -
1060 - return 0;
1061 -}
1062 -
1063 -static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
1064 -{
1065 - if (!CALIB_BUF1_VALID_V3(buf[1]))
1066 - return -EINVAL;
1067 -
1068 - mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
1069 - mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
1070 - mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
1071 - mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
1072 - mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
1073 - mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
1074 - mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
1075 -
1076 - if (CALIB_BUF1_ID_V3(buf[1]) == 0)
1077 - mt->o_slope = 0;
1078 -
1079 - return 0;
1080 -}
1081 -
1082 -static int mtk_thermal_get_calibration_data(struct device *dev,
1083 - struct mtk_thermal *mt)
1084 -{
1085 - struct nvmem_cell *cell;
1086 - u32 *buf;
1087 - size_t len;
1088 - int i, ret = 0;
1089 -
1090 - /* Start with default values */
1091 - mt->adc_ge = 512;
1092 - mt->adc_oe = 512;
1093 - for (i = 0; i < mt->conf->num_sensors; i++)
1094 - mt->vts[i] = 260;
1095 - mt->degc_cali = 40;
1096 - mt->o_slope = 0;
1097 -
1098 - cell = nvmem_cell_get(dev, "calibration-data");
1099 - if (IS_ERR(cell)) {
1100 - if (PTR_ERR(cell) == -EPROBE_DEFER)
1101 - return PTR_ERR(cell);
1102 - return 0;
1103 - }
1104 -
1105 - buf = (u32 *)nvmem_cell_read(cell, &len);
1106 -
1107 - nvmem_cell_put(cell);
1108 -
1109 - if (IS_ERR(buf))
1110 - return PTR_ERR(buf);
1111 -
1112 - if (len < 3 * sizeof(u32)) {
1113 - dev_warn(dev, "invalid calibration data\n");
1114 - ret = -EINVAL;
1115 - goto out;
1116 - }
1117 -
1118 - switch (mt->conf->version) {
1119 - case MTK_THERMAL_V1:
1120 - ret = mtk_thermal_extract_efuse_v1(mt, buf);
1121 - break;
1122 - case MTK_THERMAL_V2:
1123 - ret = mtk_thermal_extract_efuse_v2(mt, buf);
1124 - break;
1125 - case MTK_THERMAL_V3:
1126 - ret = mtk_thermal_extract_efuse_v3(mt, buf);
1127 - break;
1128 - default:
1129 - ret = -EINVAL;
1130 - break;
1131 - }
1132 -
1133 - if (ret) {
1134 - dev_info(dev, "Device not calibrated, using default calibration values\n");
1135 - ret = 0;
1136 - }
1137 -
1138 -out:
1139 - kfree(buf);
1140 -
1141 - return ret;
1142 -}
1143 -
1144 -static const struct of_device_id mtk_thermal_of_match[] = {
1145 - {
1146 - .compatible = "mediatek,mt8173-thermal",
1147 - .data = (void *)&mt8173_thermal_data,
1148 - },
1149 - {
1150 - .compatible = "mediatek,mt2701-thermal",
1151 - .data = (void *)&mt2701_thermal_data,
1152 - },
1153 - {
1154 - .compatible = "mediatek,mt2712-thermal",
1155 - .data = (void *)&mt2712_thermal_data,
1156 - },
1157 - {
1158 - .compatible = "mediatek,mt7622-thermal",
1159 - .data = (void *)&mt7622_thermal_data,
1160 - },
1161 - {
1162 - .compatible = "mediatek,mt7986-thermal",
1163 - .data = (void *)&mt7986_thermal_data,
1164 - },
1165 - {
1166 - .compatible = "mediatek,mt8183-thermal",
1167 - .data = (void *)&mt8183_thermal_data,
1168 - }, {
1169 - },
1170 -};
1171 -MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
1172 -
1173 -static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
1174 -{
1175 - int tmp;
1176 -
1177 - tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
1178 - tmp &= ~(0x37);
1179 - tmp |= 0x1;
1180 - writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
1181 - udelay(200);
1182 -}
1183 -
1184 -static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
1185 - void __iomem *auxadc_base)
1186 -{
1187 - int tmp;
1188 -
1189 - writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
1190 - writel(0x1, mt->thermal_base + TEMP_MONCTL0);
1191 - tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
1192 - writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
1193 -}
1194 -
1195 -static int mtk_thermal_probe(struct platform_device *pdev)
1196 -{
1197 - int ret, i, ctrl_id;
1198 - struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
1199 - struct mtk_thermal *mt;
1200 - u64 auxadc_phys_base, apmixed_phys_base;
1201 - struct thermal_zone_device *tzdev;
1202 - void __iomem *apmixed_base, *auxadc_base;
1203 -
1204 - mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
1205 - if (!mt)
1206 - return -ENOMEM;
1207 -
1208 - mt->conf = of_device_get_match_data(&pdev->dev);
1209 -
1210 - mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
1211 - if (IS_ERR(mt->clk_peri_therm))
1212 - return PTR_ERR(mt->clk_peri_therm);
1213 -
1214 - mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
1215 - if (IS_ERR(mt->clk_auxadc))
1216 - return PTR_ERR(mt->clk_auxadc);
1217 -
1218 - mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1219 - if (IS_ERR(mt->thermal_base))
1220 - return PTR_ERR(mt->thermal_base);
1221 -
1222 - ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
1223 - if (ret)
1224 - return ret;
1225 -
1226 - mutex_init(&mt->lock);
1227 -
1228 - mt->dev = &pdev->dev;
1229 -
1230 - auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
1231 - if (!auxadc) {
1232 - dev_err(&pdev->dev, "missing auxadc node\n");
1233 - return -ENODEV;
1234 - }
1235 -
1236 - auxadc_base = of_iomap(auxadc, 0);
1237 - auxadc_phys_base = of_get_phys_base(auxadc);
1238 -
1239 - of_node_put(auxadc);
1240 -
1241 - if (auxadc_phys_base == OF_BAD_ADDR) {
1242 - dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1243 - return -EINVAL;
1244 - }
1245 -
1246 - apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
1247 - if (!apmixedsys) {
1248 - dev_err(&pdev->dev, "missing apmixedsys node\n");
1249 - return -ENODEV;
1250 - }
1251 -
1252 - apmixed_base = of_iomap(apmixedsys, 0);
1253 - apmixed_phys_base = of_get_phys_base(apmixedsys);
1254 -
1255 - of_node_put(apmixedsys);
1256 -
1257 - if (apmixed_phys_base == OF_BAD_ADDR) {
1258 - dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1259 - return -EINVAL;
1260 - }
1261 -
1262 - ret = device_reset_optional(&pdev->dev);
1263 - if (ret)
1264 - return ret;
1265 -
1266 - ret = clk_prepare_enable(mt->clk_auxadc);
1267 - if (ret) {
1268 - dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
1269 - return ret;
1270 - }
1271 -
1272 - ret = clk_prepare_enable(mt->clk_peri_therm);
1273 - if (ret) {
1274 - dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
1275 - goto err_disable_clk_auxadc;
1276 - }
1277 -
1278 - if (mt->conf->version != MTK_THERMAL_V1) {
1279 - mtk_thermal_turn_on_buffer(apmixed_base);
1280 - mtk_thermal_release_periodic_ts(mt, auxadc_base);
1281 - }
1282 -
1283 - if (mt->conf->version == MTK_THERMAL_V1)
1284 - mt->raw_to_mcelsius = raw_to_mcelsius_v1;
1285 - else if (mt->conf->version == MTK_THERMAL_V2)
1286 - mt->raw_to_mcelsius = raw_to_mcelsius_v2;
1287 - else
1288 - mt->raw_to_mcelsius = raw_to_mcelsius_v3;
1289 -
1290 - for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
1291 - for (i = 0; i < mt->conf->num_banks; i++)
1292 - mtk_thermal_init_bank(mt, i, apmixed_phys_base,
1293 - auxadc_phys_base, ctrl_id);
1294 -
1295 - platform_set_drvdata(pdev, mt);
1296 -
1297 - tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
1298 - &mtk_thermal_ops);
1299 - if (IS_ERR(tzdev)) {
1300 - ret = PTR_ERR(tzdev);
1301 - goto err_disable_clk_peri_therm;
1302 - }
1303 -
1304 - ret = devm_thermal_add_hwmon_sysfs(tzdev);
1305 - if (ret)
1306 - dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
1307 -
1308 - return 0;
1309 -
1310 -err_disable_clk_peri_therm:
1311 - clk_disable_unprepare(mt->clk_peri_therm);
1312 -err_disable_clk_auxadc:
1313 - clk_disable_unprepare(mt->clk_auxadc);
1314 -
1315 - return ret;
1316 -}
1317 -
1318 -static int mtk_thermal_remove(struct platform_device *pdev)
1319 -{
1320 - struct mtk_thermal *mt = platform_get_drvdata(pdev);
1321 -
1322 - clk_disable_unprepare(mt->clk_peri_therm);
1323 - clk_disable_unprepare(mt->clk_auxadc);
1324 -
1325 - return 0;
1326 -}
1327 -
1328 -static struct platform_driver mtk_thermal_driver = {
1329 - .probe = mtk_thermal_probe,
1330 - .remove = mtk_thermal_remove,
1331 - .driver = {
1332 - .name = "mtk-thermal",
1333 - .of_match_table = mtk_thermal_of_match,
1334 - },
1335 -};
1336 -
1337 -module_platform_driver(mtk_thermal_driver);
1338 -
1339 -MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
1340 -MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
1341 -MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
1342 -MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1343 -MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
1344 -MODULE_DESCRIPTION("Mediatek thermal driver");
1345 -MODULE_LICENSE("GPL v2");
1346 --- /dev/null
1347 +++ b/drivers/thermal/mediatek/auxadc_thermal.c
1348 @@ -0,0 +1,1254 @@
1349 +// SPDX-License-Identifier: GPL-2.0-only
1350 +/*
1351 + * Copyright (c) 2015 MediaTek Inc.
1352 + * Author: Hanyi Wu <hanyi.wu@mediatek.com>
1353 + * Sascha Hauer <s.hauer@pengutronix.de>
1354 + * Dawei Chien <dawei.chien@mediatek.com>
1355 + * Louis Yu <louis.yu@mediatek.com>
1356 + */
1357 +
1358 +#include <linux/clk.h>
1359 +#include <linux/delay.h>
1360 +#include <linux/interrupt.h>
1361 +#include <linux/kernel.h>
1362 +#include <linux/module.h>
1363 +#include <linux/nvmem-consumer.h>
1364 +#include <linux/of.h>
1365 +#include <linux/of_address.h>
1366 +#include <linux/of_device.h>
1367 +#include <linux/platform_device.h>
1368 +#include <linux/slab.h>
1369 +#include <linux/io.h>
1370 +#include <linux/thermal.h>
1371 +#include <linux/reset.h>
1372 +#include <linux/types.h>
1373 +
1374 +#include "../thermal_hwmon.h"
1375 +
1376 +/* AUXADC Registers */
1377 +#define AUXADC_CON1_SET_V 0x008
1378 +#define AUXADC_CON1_CLR_V 0x00c
1379 +#define AUXADC_CON2_V 0x010
1380 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
1381 +
1382 +#define APMIXED_SYS_TS_CON1 0x604
1383 +
1384 +/* Thermal Controller Registers */
1385 +#define TEMP_MONCTL0 0x000
1386 +#define TEMP_MONCTL1 0x004
1387 +#define TEMP_MONCTL2 0x008
1388 +#define TEMP_MONIDET0 0x014
1389 +#define TEMP_MONIDET1 0x018
1390 +#define TEMP_MSRCTL0 0x038
1391 +#define TEMP_MSRCTL1 0x03c
1392 +#define TEMP_AHBPOLL 0x040
1393 +#define TEMP_AHBTO 0x044
1394 +#define TEMP_ADCPNP0 0x048
1395 +#define TEMP_ADCPNP1 0x04c
1396 +#define TEMP_ADCPNP2 0x050
1397 +#define TEMP_ADCPNP3 0x0b4
1398 +
1399 +#define TEMP_ADCMUX 0x054
1400 +#define TEMP_ADCEN 0x060
1401 +#define TEMP_PNPMUXADDR 0x064
1402 +#define TEMP_ADCMUXADDR 0x068
1403 +#define TEMP_ADCENADDR 0x074
1404 +#define TEMP_ADCVALIDADDR 0x078
1405 +#define TEMP_ADCVOLTADDR 0x07c
1406 +#define TEMP_RDCTRL 0x080
1407 +#define TEMP_ADCVALIDMASK 0x084
1408 +#define TEMP_ADCVOLTAGESHIFT 0x088
1409 +#define TEMP_ADCWRITECTRL 0x08c
1410 +#define TEMP_MSR0 0x090
1411 +#define TEMP_MSR1 0x094
1412 +#define TEMP_MSR2 0x098
1413 +#define TEMP_MSR3 0x0B8
1414 +
1415 +#define TEMP_SPARE0 0x0f0
1416 +
1417 +#define TEMP_ADCPNP0_1 0x148
1418 +#define TEMP_ADCPNP1_1 0x14c
1419 +#define TEMP_ADCPNP2_1 0x150
1420 +#define TEMP_MSR0_1 0x190
1421 +#define TEMP_MSR1_1 0x194
1422 +#define TEMP_MSR2_1 0x198
1423 +#define TEMP_ADCPNP3_1 0x1b4
1424 +#define TEMP_MSR3_1 0x1B8
1425 +
1426 +#define PTPCORESEL 0x400
1427 +
1428 +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
1429 +
1430 +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
1431 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
1432 +
1433 +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
1434 +
1435 +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
1436 +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
1437 +
1438 +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
1439 +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
1440 +
1441 +/* MT8173 thermal sensors */
1442 +#define MT8173_TS1 0
1443 +#define MT8173_TS2 1
1444 +#define MT8173_TS3 2
1445 +#define MT8173_TS4 3
1446 +#define MT8173_TSABB 4
1447 +
1448 +/* AUXADC channel 11 is used for the temperature sensors */
1449 +#define MT8173_TEMP_AUXADC_CHANNEL 11
1450 +
1451 +/* The total number of temperature sensors in the MT8173 */
1452 +#define MT8173_NUM_SENSORS 5
1453 +
1454 +/* The number of banks in the MT8173 */
1455 +#define MT8173_NUM_ZONES 4
1456 +
1457 +/* The number of sensing points per bank */
1458 +#define MT8173_NUM_SENSORS_PER_ZONE 4
1459 +
1460 +/* The number of controller in the MT8173 */
1461 +#define MT8173_NUM_CONTROLLER 1
1462 +
1463 +/* The calibration coefficient of sensor */
1464 +#define MT8173_CALIBRATION 165
1465 +
1466 +/*
1467 + * Layout of the fuses providing the calibration data
1468 + * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
1469 + * MT8183 has 6 sensors and needs 6 VTS calibration data.
1470 + * MT8173 has 5 sensors and needs 5 VTS calibration data.
1471 + * MT2701 has 3 sensors and needs 3 VTS calibration data.
1472 + * MT2712 has 4 sensors and needs 4 VTS calibration data.
1473 + */
1474 +#define CALIB_BUF0_VALID_V1 BIT(0)
1475 +#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
1476 +#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
1477 +#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
1478 +#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
1479 +#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
1480 +#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
1481 +#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
1482 +#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
1483 +#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
1484 +#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
1485 +#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
1486 +
1487 +/*
1488 + * Layout of the fuses providing the calibration data
1489 + * These macros could be used for MT7622.
1490 + */
1491 +#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
1492 +#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
1493 +#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
1494 +#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
1495 +#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
1496 +#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
1497 +#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
1498 +#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
1499 +#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
1500 +
1501 +/*
1502 + * Layout of the fuses providing the calibration data
1503 + * These macros can be used for MT7981 and MT7986.
1504 + */
1505 +#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
1506 +#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
1507 +#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
1508 +#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
1509 +#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
1510 +#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
1511 +#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
1512 +#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
1513 +#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
1514 +
1515 +enum {
1516 + VTS1,
1517 + VTS2,
1518 + VTS3,
1519 + VTS4,
1520 + VTS5,
1521 + VTSABB,
1522 + MAX_NUM_VTS,
1523 +};
1524 +
1525 +enum mtk_thermal_version {
1526 + MTK_THERMAL_V1 = 1,
1527 + MTK_THERMAL_V2,
1528 + MTK_THERMAL_V3,
1529 +};
1530 +
1531 +/* MT2701 thermal sensors */
1532 +#define MT2701_TS1 0
1533 +#define MT2701_TS2 1
1534 +#define MT2701_TSABB 2
1535 +
1536 +/* AUXADC channel 11 is used for the temperature sensors */
1537 +#define MT2701_TEMP_AUXADC_CHANNEL 11
1538 +
1539 +/* The total number of temperature sensors in the MT2701 */
1540 +#define MT2701_NUM_SENSORS 3
1541 +
1542 +/* The number of sensing points per bank */
1543 +#define MT2701_NUM_SENSORS_PER_ZONE 3
1544 +
1545 +/* The number of controller in the MT2701 */
1546 +#define MT2701_NUM_CONTROLLER 1
1547 +
1548 +/* The calibration coefficient of sensor */
1549 +#define MT2701_CALIBRATION 165
1550 +
1551 +/* MT2712 thermal sensors */
1552 +#define MT2712_TS1 0
1553 +#define MT2712_TS2 1
1554 +#define MT2712_TS3 2
1555 +#define MT2712_TS4 3
1556 +
1557 +/* AUXADC channel 11 is used for the temperature sensors */
1558 +#define MT2712_TEMP_AUXADC_CHANNEL 11
1559 +
1560 +/* The total number of temperature sensors in the MT2712 */
1561 +#define MT2712_NUM_SENSORS 4
1562 +
1563 +/* The number of sensing points per bank */
1564 +#define MT2712_NUM_SENSORS_PER_ZONE 4
1565 +
1566 +/* The number of controller in the MT2712 */
1567 +#define MT2712_NUM_CONTROLLER 1
1568 +
1569 +/* The calibration coefficient of sensor */
1570 +#define MT2712_CALIBRATION 165
1571 +
1572 +#define MT7622_TEMP_AUXADC_CHANNEL 11
1573 +#define MT7622_NUM_SENSORS 1
1574 +#define MT7622_NUM_ZONES 1
1575 +#define MT7622_NUM_SENSORS_PER_ZONE 1
1576 +#define MT7622_TS1 0
1577 +#define MT7622_NUM_CONTROLLER 1
1578 +
1579 +/* The maximum number of banks */
1580 +#define MAX_NUM_ZONES 8
1581 +
1582 +/* The calibration coefficient of sensor */
1583 +#define MT7622_CALIBRATION 165
1584 +
1585 +/* MT8183 thermal sensors */
1586 +#define MT8183_TS1 0
1587 +#define MT8183_TS2 1
1588 +#define MT8183_TS3 2
1589 +#define MT8183_TS4 3
1590 +#define MT8183_TS5 4
1591 +#define MT8183_TSABB 5
1592 +
1593 +/* AUXADC channel is used for the temperature sensors */
1594 +#define MT8183_TEMP_AUXADC_CHANNEL 11
1595 +
1596 +/* The total number of temperature sensors in the MT8183 */
1597 +#define MT8183_NUM_SENSORS 6
1598 +
1599 +/* The number of banks in the MT8183 */
1600 +#define MT8183_NUM_ZONES 1
1601 +
1602 +/* The number of sensing points per bank */
1603 +#define MT8183_NUM_SENSORS_PER_ZONE 6
1604 +
1605 +/* The number of controller in the MT8183 */
1606 +#define MT8183_NUM_CONTROLLER 2
1607 +
1608 +/* The calibration coefficient of sensor */
1609 +#define MT8183_CALIBRATION 153
1610 +
1611 +/* AUXADC channel 11 is used for the temperature sensors */
1612 +#define MT7986_TEMP_AUXADC_CHANNEL 11
1613 +
1614 +/* The total number of temperature sensors in the MT7986 */
1615 +#define MT7986_NUM_SENSORS 1
1616 +
1617 +/* The number of banks in the MT7986 */
1618 +#define MT7986_NUM_ZONES 1
1619 +
1620 +/* The number of sensing points per bank */
1621 +#define MT7986_NUM_SENSORS_PER_ZONE 1
1622 +
1623 +/* MT7986 thermal sensors */
1624 +#define MT7986_TS1 0
1625 +
1626 +/* The number of controller in the MT7986 */
1627 +#define MT7986_NUM_CONTROLLER 1
1628 +
1629 +/* The calibration coefficient of sensor */
1630 +#define MT7986_CALIBRATION 165
1631 +
1632 +struct mtk_thermal;
1633 +
1634 +struct thermal_bank_cfg {
1635 + unsigned int num_sensors;
1636 + const int *sensors;
1637 +};
1638 +
1639 +struct mtk_thermal_bank {
1640 + struct mtk_thermal *mt;
1641 + int id;
1642 +};
1643 +
1644 +struct mtk_thermal_data {
1645 + s32 num_banks;
1646 + s32 num_sensors;
1647 + s32 auxadc_channel;
1648 + const int *vts_index;
1649 + const int *sensor_mux_values;
1650 + const int *msr;
1651 + const int *adcpnp;
1652 + const int cali_val;
1653 + const int num_controller;
1654 + const int *controller_offset;
1655 + bool need_switch_bank;
1656 + struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
1657 + enum mtk_thermal_version version;
1658 +};
1659 +
1660 +struct mtk_thermal {
1661 + struct device *dev;
1662 + void __iomem *thermal_base;
1663 +
1664 + struct clk *clk_peri_therm;
1665 + struct clk *clk_auxadc;
1666 + /* lock: for getting and putting banks */
1667 + struct mutex lock;
1668 +
1669 + /* Calibration values */
1670 + s32 adc_ge;
1671 + s32 adc_oe;
1672 + s32 degc_cali;
1673 + s32 o_slope;
1674 + s32 o_slope_sign;
1675 + s32 vts[MAX_NUM_VTS];
1676 +
1677 + const struct mtk_thermal_data *conf;
1678 + struct mtk_thermal_bank banks[MAX_NUM_ZONES];
1679 +
1680 + int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
1681 +};
1682 +
1683 +/* MT8183 thermal sensor data */
1684 +static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
1685 + MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
1686 +};
1687 +
1688 +static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
1689 + TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
1690 +};
1691 +
1692 +static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
1693 + TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
1694 + TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
1695 +};
1696 +
1697 +static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
1698 +static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
1699 +
1700 +static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
1701 + VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
1702 +};
1703 +
1704 +/* MT8173 thermal sensor data */
1705 +static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
1706 + { MT8173_TS2, MT8173_TS3 },
1707 + { MT8173_TS2, MT8173_TS4 },
1708 + { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
1709 + { MT8173_TS2 },
1710 +};
1711 +
1712 +static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
1713 + TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
1714 +};
1715 +
1716 +static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
1717 + TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
1718 +};
1719 +
1720 +static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
1721 +static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
1722 +
1723 +static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
1724 + VTS1, VTS2, VTS3, VTS4, VTSABB
1725 +};
1726 +
1727 +/* MT2701 thermal sensor data */
1728 +static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
1729 + MT2701_TS1, MT2701_TS2, MT2701_TSABB
1730 +};
1731 +
1732 +static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
1733 + TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
1734 +};
1735 +
1736 +static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
1737 + TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
1738 +};
1739 +
1740 +static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
1741 +static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
1742 +
1743 +static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
1744 + VTS1, VTS2, VTS3
1745 +};
1746 +
1747 +/* MT2712 thermal sensor data */
1748 +static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
1749 + MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
1750 +};
1751 +
1752 +static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
1753 + TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
1754 +};
1755 +
1756 +static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
1757 + TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
1758 +};
1759 +
1760 +static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
1761 +static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
1762 +
1763 +static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
1764 + VTS1, VTS2, VTS3, VTS4
1765 +};
1766 +
1767 +/* MT7622 thermal sensor data */
1768 +static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
1769 +static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
1770 +static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
1771 +static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
1772 +static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
1773 +static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
1774 +
1775 +/* MT7986 thermal sensor data */
1776 +static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
1777 +static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
1778 +static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
1779 +static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
1780 +static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
1781 +static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
1782 +
1783 +/*
1784 + * The MT8173 thermal controller has four banks. Each bank can read up to
1785 + * four temperature sensors simultaneously. The MT8173 has a total of 5
1786 + * temperature sensors. We use each bank to measure a certain area of the
1787 + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
1788 + * areas, hence is used in different banks.
1789 + *
1790 + * The thermal core only gets the maximum temperature of all banks, so
1791 + * the bank concept wouldn't be necessary here. However, the SVS (Smart
1792 + * Voltage Scaling) unit makes its decisions based on the same bank
1793 + * data, and this indeed needs the temperatures of the individual banks
1794 + * for making better decisions.
1795 + */
1796 +static const struct mtk_thermal_data mt8173_thermal_data = {
1797 + .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
1798 + .num_banks = MT8173_NUM_ZONES,
1799 + .num_sensors = MT8173_NUM_SENSORS,
1800 + .vts_index = mt8173_vts_index,
1801 + .cali_val = MT8173_CALIBRATION,
1802 + .num_controller = MT8173_NUM_CONTROLLER,
1803 + .controller_offset = mt8173_tc_offset,
1804 + .need_switch_bank = true,
1805 + .bank_data = {
1806 + {
1807 + .num_sensors = 2,
1808 + .sensors = mt8173_bank_data[0],
1809 + }, {
1810 + .num_sensors = 2,
1811 + .sensors = mt8173_bank_data[1],
1812 + }, {
1813 + .num_sensors = 3,
1814 + .sensors = mt8173_bank_data[2],
1815 + }, {
1816 + .num_sensors = 1,
1817 + .sensors = mt8173_bank_data[3],
1818 + },
1819 + },
1820 + .msr = mt8173_msr,
1821 + .adcpnp = mt8173_adcpnp,
1822 + .sensor_mux_values = mt8173_mux_values,
1823 + .version = MTK_THERMAL_V1,
1824 +};
1825 +
1826 +/*
1827 + * The MT2701 thermal controller has one bank, which can read up to
1828 + * three temperature sensors simultaneously. The MT2701 has a total of 3
1829 + * temperature sensors.
1830 + *
1831 + * The thermal core only gets the maximum temperature of this one bank,
1832 + * so the bank concept wouldn't be necessary here. However, the SVS (Smart
1833 + * Voltage Scaling) unit makes its decisions based on the same bank
1834 + * data.
1835 + */
1836 +static const struct mtk_thermal_data mt2701_thermal_data = {
1837 + .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
1838 + .num_banks = 1,
1839 + .num_sensors = MT2701_NUM_SENSORS,
1840 + .vts_index = mt2701_vts_index,
1841 + .cali_val = MT2701_CALIBRATION,
1842 + .num_controller = MT2701_NUM_CONTROLLER,
1843 + .controller_offset = mt2701_tc_offset,
1844 + .need_switch_bank = true,
1845 + .bank_data = {
1846 + {
1847 + .num_sensors = 3,
1848 + .sensors = mt2701_bank_data,
1849 + },
1850 + },
1851 + .msr = mt2701_msr,
1852 + .adcpnp = mt2701_adcpnp,
1853 + .sensor_mux_values = mt2701_mux_values,
1854 + .version = MTK_THERMAL_V1,
1855 +};
1856 +
1857 +/*
1858 + * The MT2712 thermal controller has one bank, which can read up to
1859 + * four temperature sensors simultaneously. The MT2712 has a total of 4
1860 + * temperature sensors.
1861 + *
1862 + * The thermal core only gets the maximum temperature of this one bank,
1863 + * so the bank concept wouldn't be necessary here. However, the SVS (Smart
1864 + * Voltage Scaling) unit makes its decisions based on the same bank
1865 + * data.
1866 + */
1867 +static const struct mtk_thermal_data mt2712_thermal_data = {
1868 + .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
1869 + .num_banks = 1,
1870 + .num_sensors = MT2712_NUM_SENSORS,
1871 + .vts_index = mt2712_vts_index,
1872 + .cali_val = MT2712_CALIBRATION,
1873 + .num_controller = MT2712_NUM_CONTROLLER,
1874 + .controller_offset = mt2712_tc_offset,
1875 + .need_switch_bank = true,
1876 + .bank_data = {
1877 + {
1878 + .num_sensors = 4,
1879 + .sensors = mt2712_bank_data,
1880 + },
1881 + },
1882 + .msr = mt2712_msr,
1883 + .adcpnp = mt2712_adcpnp,
1884 + .sensor_mux_values = mt2712_mux_values,
1885 + .version = MTK_THERMAL_V1,
1886 +};
1887 +
1888 +/*
1889 + * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
1890 + * access.
1891 + */
1892 +static const struct mtk_thermal_data mt7622_thermal_data = {
1893 + .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
1894 + .num_banks = MT7622_NUM_ZONES,
1895 + .num_sensors = MT7622_NUM_SENSORS,
1896 + .vts_index = mt7622_vts_index,
1897 + .cali_val = MT7622_CALIBRATION,
1898 + .num_controller = MT7622_NUM_CONTROLLER,
1899 + .controller_offset = mt7622_tc_offset,
1900 + .need_switch_bank = true,
1901 + .bank_data = {
1902 + {
1903 + .num_sensors = 1,
1904 + .sensors = mt7622_bank_data,
1905 + },
1906 + },
1907 + .msr = mt7622_msr,
1908 + .adcpnp = mt7622_adcpnp,
1909 + .sensor_mux_values = mt7622_mux_values,
1910 + .version = MTK_THERMAL_V2,
1911 +};
1912 +
1913 +/*
1914 + * The MT8183 thermal controller has one bank for the current SW framework.
1915 + * The MT8183 has a total of 6 temperature sensors.
1916 + * There are two thermal controller to control the six sensor.
1917 + * The first one bind 2 sensor, and the other bind 4 sensors.
1918 + * The thermal core only gets the maximum temperature of all sensor, so
1919 + * the bank concept wouldn't be necessary here. However, the SVS (Smart
1920 + * Voltage Scaling) unit makes its decisions based on the same bank
1921 + * data, and this indeed needs the temperatures of the individual banks
1922 + * for making better decisions.
1923 + */
1924 +static const struct mtk_thermal_data mt8183_thermal_data = {
1925 + .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
1926 + .num_banks = MT8183_NUM_ZONES,
1927 + .num_sensors = MT8183_NUM_SENSORS,
1928 + .vts_index = mt8183_vts_index,
1929 + .cali_val = MT8183_CALIBRATION,
1930 + .num_controller = MT8183_NUM_CONTROLLER,
1931 + .controller_offset = mt8183_tc_offset,
1932 + .need_switch_bank = false,
1933 + .bank_data = {
1934 + {
1935 + .num_sensors = 6,
1936 + .sensors = mt8183_bank_data,
1937 + },
1938 + },
1939 +
1940 + .msr = mt8183_msr,
1941 + .adcpnp = mt8183_adcpnp,
1942 + .sensor_mux_values = mt8183_mux_values,
1943 + .version = MTK_THERMAL_V1,
1944 +};
1945 +
1946 +/*
1947 + * MT7986 uses AUXADC Channel 11 for raw data access.
1948 + */
1949 +static const struct mtk_thermal_data mt7986_thermal_data = {
1950 + .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
1951 + .num_banks = MT7986_NUM_ZONES,
1952 + .num_sensors = MT7986_NUM_SENSORS,
1953 + .vts_index = mt7986_vts_index,
1954 + .cali_val = MT7986_CALIBRATION,
1955 + .num_controller = MT7986_NUM_CONTROLLER,
1956 + .controller_offset = mt7986_tc_offset,
1957 + .need_switch_bank = true,
1958 + .bank_data = {
1959 + {
1960 + .num_sensors = 1,
1961 + .sensors = mt7986_bank_data,
1962 + },
1963 + },
1964 + .msr = mt7986_msr,
1965 + .adcpnp = mt7986_adcpnp,
1966 + .sensor_mux_values = mt7986_mux_values,
1967 + .version = MTK_THERMAL_V3,
1968 +};
1969 +
1970 +/**
1971 + * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
1972 + * @mt: The thermal controller
1973 + * @sensno: sensor number
1974 + * @raw: raw ADC value
1975 + *
1976 + * This converts the raw ADC value to mcelsius using the SoC specific
1977 + * calibration constants
1978 + */
1979 +static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
1980 +{
1981 + s32 tmp;
1982 +
1983 + raw &= 0xfff;
1984 +
1985 + tmp = 203450520 << 3;
1986 + tmp /= mt->conf->cali_val + mt->o_slope;
1987 + tmp /= 10000 + mt->adc_ge;
1988 + tmp *= raw - mt->vts[sensno] - 3350;
1989 + tmp >>= 3;
1990 +
1991 + return mt->degc_cali * 500 - tmp;
1992 +}
1993 +
1994 +static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
1995 +{
1996 + s32 format_1;
1997 + s32 format_2;
1998 + s32 g_oe;
1999 + s32 g_gain;
2000 + s32 g_x_roomt;
2001 + s32 tmp;
2002 +
2003 + if (raw == 0)
2004 + return 0;
2005 +
2006 + raw &= 0xfff;
2007 + g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
2008 + g_oe = mt->adc_oe - 512;
2009 + format_1 = mt->vts[VTS2] + 3105 - g_oe;
2010 + format_2 = (mt->degc_cali * 10) >> 1;
2011 + g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
2012 +
2013 + tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
2014 + tmp = tmp * 10 * 100 / 11;
2015 +
2016 + if (mt->o_slope_sign == 0)
2017 + tmp = tmp / (165 - mt->o_slope);
2018 + else
2019 + tmp = tmp / (165 + mt->o_slope);
2020 +
2021 + return (format_2 - tmp) * 100;
2022 +}
2023 +
2024 +static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
2025 +{
2026 + s32 tmp;
2027 +
2028 + if (raw == 0)
2029 + return 0;
2030 +
2031 + raw &= 0xfff;
2032 + tmp = 100000 * 15 / 16 * 10000;
2033 + tmp /= 4096 - 512 + mt->adc_ge;
2034 + tmp /= 1490;
2035 + tmp *= raw - mt->vts[sensno] - 2900;
2036 +
2037 + return mt->degc_cali * 500 - tmp;
2038 +}
2039 +
2040 +/**
2041 + * mtk_thermal_get_bank - get bank
2042 + * @bank: The bank
2043 + *
2044 + * The bank registers are banked, we have to select a bank in the
2045 + * PTPCORESEL register to access it.
2046 + */
2047 +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
2048 +{
2049 + struct mtk_thermal *mt = bank->mt;
2050 + u32 val;
2051 +
2052 + if (mt->conf->need_switch_bank) {
2053 + mutex_lock(&mt->lock);
2054 +
2055 + val = readl(mt->thermal_base + PTPCORESEL);
2056 + val &= ~0xf;
2057 + val |= bank->id;
2058 + writel(val, mt->thermal_base + PTPCORESEL);
2059 + }
2060 +}
2061 +
2062 +/**
2063 + * mtk_thermal_put_bank - release bank
2064 + * @bank: The bank
2065 + *
2066 + * release a bank previously taken with mtk_thermal_get_bank,
2067 + */
2068 +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
2069 +{
2070 + struct mtk_thermal *mt = bank->mt;
2071 +
2072 + if (mt->conf->need_switch_bank)
2073 + mutex_unlock(&mt->lock);
2074 +}
2075 +
2076 +/**
2077 + * mtk_thermal_bank_temperature - get the temperature of a bank
2078 + * @bank: The bank
2079 + *
2080 + * The temperature of a bank is considered the maximum temperature of
2081 + * the sensors associated to the bank.
2082 + */
2083 +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
2084 +{
2085 + struct mtk_thermal *mt = bank->mt;
2086 + const struct mtk_thermal_data *conf = mt->conf;
2087 + int i, temp = INT_MIN, max = INT_MIN;
2088 + u32 raw;
2089 +
2090 + for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
2091 + raw = readl(mt->thermal_base + conf->msr[i]);
2092 +
2093 + temp = mt->raw_to_mcelsius(
2094 + mt, conf->bank_data[bank->id].sensors[i], raw);
2095 +
2096 +
2097 + /*
2098 + * The first read of a sensor often contains very high bogus
2099 + * temperature value. Filter these out so that the system does
2100 + * not immediately shut down.
2101 + */
2102 + if (temp > 200000)
2103 + temp = 0;
2104 +
2105 + if (temp > max)
2106 + max = temp;
2107 + }
2108 +
2109 + return max;
2110 +}
2111 +
2112 +static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
2113 +{
2114 + struct mtk_thermal *mt = tz->devdata;
2115 + int i;
2116 + int tempmax = INT_MIN;
2117 +
2118 + for (i = 0; i < mt->conf->num_banks; i++) {
2119 + struct mtk_thermal_bank *bank = &mt->banks[i];
2120 +
2121 + mtk_thermal_get_bank(bank);
2122 +
2123 + tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
2124 +
2125 + mtk_thermal_put_bank(bank);
2126 + }
2127 +
2128 + *temperature = tempmax;
2129 +
2130 + return 0;
2131 +}
2132 +
2133 +static const struct thermal_zone_device_ops mtk_thermal_ops = {
2134 + .get_temp = mtk_read_temp,
2135 +};
2136 +
2137 +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
2138 + u32 apmixed_phys_base, u32 auxadc_phys_base,
2139 + int ctrl_id)
2140 +{
2141 + struct mtk_thermal_bank *bank = &mt->banks[num];
2142 + const struct mtk_thermal_data *conf = mt->conf;
2143 + int i;
2144 +
2145 + int offset = mt->conf->controller_offset[ctrl_id];
2146 + void __iomem *controller_base = mt->thermal_base + offset;
2147 +
2148 + bank->id = num;
2149 + bank->mt = mt;
2150 +
2151 + mtk_thermal_get_bank(bank);
2152 +
2153 + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
2154 + writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
2155 +
2156 + /*
2157 + * filt interval is 1 * 46.540us = 46.54us,
2158 + * sen interval is 429 * 46.540us = 19.96ms
2159 + */
2160 + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
2161 + TEMP_MONCTL2_SENSOR_INTERVAL(429),
2162 + controller_base + TEMP_MONCTL2);
2163 +
2164 + /* poll is set to 10u */
2165 + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
2166 + controller_base + TEMP_AHBPOLL);
2167 +
2168 + /* temperature sampling control, 1 sample */
2169 + writel(0x0, controller_base + TEMP_MSRCTL0);
2170 +
2171 + /* exceed this polling time, IRQ would be inserted */
2172 + writel(0xffffffff, controller_base + TEMP_AHBTO);
2173 +
2174 + /* number of interrupts per event, 1 is enough */
2175 + writel(0x0, controller_base + TEMP_MONIDET0);
2176 + writel(0x0, controller_base + TEMP_MONIDET1);
2177 +
2178 + /*
2179 + * The MT8173 thermal controller does not have its own ADC. Instead it
2180 + * uses AHB bus accesses to control the AUXADC. To do this the thermal
2181 + * controller has to be programmed with the physical addresses of the
2182 + * AUXADC registers and with the various bit positions in the AUXADC.
2183 + * Also the thermal controller controls a mux in the APMIXEDSYS register
2184 + * space.
2185 + */
2186 +
2187 + /*
2188 + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
2189 + * automatically by hw
2190 + */
2191 + writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
2192 +
2193 + /* AHB address for auxadc mux selection */
2194 + writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
2195 + controller_base + TEMP_ADCMUXADDR);
2196 +
2197 + if (mt->conf->version == MTK_THERMAL_V1) {
2198 + /* AHB address for pnp sensor mux selection */
2199 + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
2200 + controller_base + TEMP_PNPMUXADDR);
2201 + }
2202 +
2203 + /* AHB value for auxadc enable */
2204 + writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
2205 +
2206 + /* AHB address for auxadc enable (channel 0 immediate mode selected) */
2207 + writel(auxadc_phys_base + AUXADC_CON1_SET_V,
2208 + controller_base + TEMP_ADCENADDR);
2209 +
2210 + /* AHB address for auxadc valid bit */
2211 + writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
2212 + controller_base + TEMP_ADCVALIDADDR);
2213 +
2214 + /* AHB address for auxadc voltage output */
2215 + writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
2216 + controller_base + TEMP_ADCVOLTADDR);
2217 +
2218 + /* read valid & voltage are at the same register */
2219 + writel(0x0, controller_base + TEMP_RDCTRL);
2220 +
2221 + /* indicate where the valid bit is */
2222 + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
2223 + controller_base + TEMP_ADCVALIDMASK);
2224 +
2225 + /* no shift */
2226 + writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
2227 +
2228 + /* enable auxadc mux write transaction */
2229 + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
2230 + controller_base + TEMP_ADCWRITECTRL);
2231 +
2232 + for (i = 0; i < conf->bank_data[num].num_sensors; i++)
2233 + writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
2234 + mt->thermal_base + conf->adcpnp[i]);
2235 +
2236 + writel((1 << conf->bank_data[num].num_sensors) - 1,
2237 + controller_base + TEMP_MONCTL0);
2238 +
2239 + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
2240 + TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
2241 + controller_base + TEMP_ADCWRITECTRL);
2242 +
2243 + mtk_thermal_put_bank(bank);
2244 +}
2245 +
2246 +static u64 of_get_phys_base(struct device_node *np)
2247 +{
2248 + u64 size64;
2249 + const __be32 *regaddr_p;
2250 +
2251 + regaddr_p = of_get_address(np, 0, &size64, NULL);
2252 + if (!regaddr_p)
2253 + return OF_BAD_ADDR;
2254 +
2255 + return of_translate_address(np, regaddr_p);
2256 +}
2257 +
2258 +static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
2259 +{
2260 + int i;
2261 +
2262 + if (!(buf[0] & CALIB_BUF0_VALID_V1))
2263 + return -EINVAL;
2264 +
2265 + mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
2266 +
2267 + for (i = 0; i < mt->conf->num_sensors; i++) {
2268 + switch (mt->conf->vts_index[i]) {
2269 + case VTS1:
2270 + mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
2271 + break;
2272 + case VTS2:
2273 + mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
2274 + break;
2275 + case VTS3:
2276 + mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
2277 + break;
2278 + case VTS4:
2279 + mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
2280 + break;
2281 + case VTS5:
2282 + mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
2283 + break;
2284 + case VTSABB:
2285 + mt->vts[VTSABB] =
2286 + CALIB_BUF2_VTS_TSABB_V1(buf[2]);
2287 + break;
2288 + default:
2289 + break;
2290 + }
2291 + }
2292 +
2293 + mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
2294 + if (CALIB_BUF1_ID_V1(buf[1]) &
2295 + CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
2296 + mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
2297 + else
2298 + mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
2299 +
2300 + return 0;
2301 +}
2302 +
2303 +static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
2304 +{
2305 + if (!CALIB_BUF1_VALID_V2(buf[1]))
2306 + return -EINVAL;
2307 +
2308 + mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
2309 + mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
2310 + mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
2311 + mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
2312 + mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
2313 + mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
2314 + mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
2315 + mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
2316 +
2317 + return 0;
2318 +}
2319 +
2320 +static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
2321 +{
2322 + if (!CALIB_BUF1_VALID_V3(buf[1]))
2323 + return -EINVAL;
2324 +
2325 + mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
2326 + mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
2327 + mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
2328 + mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
2329 + mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
2330 + mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
2331 + mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
2332 +
2333 + if (CALIB_BUF1_ID_V3(buf[1]) == 0)
2334 + mt->o_slope = 0;
2335 +
2336 + return 0;
2337 +}
2338 +
2339 +static int mtk_thermal_get_calibration_data(struct device *dev,
2340 + struct mtk_thermal *mt)
2341 +{
2342 + struct nvmem_cell *cell;
2343 + u32 *buf;
2344 + size_t len;
2345 + int i, ret = 0;
2346 +
2347 + /* Start with default values */
2348 + mt->adc_ge = 512;
2349 + mt->adc_oe = 512;
2350 + for (i = 0; i < mt->conf->num_sensors; i++)
2351 + mt->vts[i] = 260;
2352 + mt->degc_cali = 40;
2353 + mt->o_slope = 0;
2354 +
2355 + cell = nvmem_cell_get(dev, "calibration-data");
2356 + if (IS_ERR(cell)) {
2357 + if (PTR_ERR(cell) == -EPROBE_DEFER)
2358 + return PTR_ERR(cell);
2359 + return 0;
2360 + }
2361 +
2362 + buf = (u32 *)nvmem_cell_read(cell, &len);
2363 +
2364 + nvmem_cell_put(cell);
2365 +
2366 + if (IS_ERR(buf))
2367 + return PTR_ERR(buf);
2368 +
2369 + if (len < 3 * sizeof(u32)) {
2370 + dev_warn(dev, "invalid calibration data\n");
2371 + ret = -EINVAL;
2372 + goto out;
2373 + }
2374 +
2375 + switch (mt->conf->version) {
2376 + case MTK_THERMAL_V1:
2377 + ret = mtk_thermal_extract_efuse_v1(mt, buf);
2378 + break;
2379 + case MTK_THERMAL_V2:
2380 + ret = mtk_thermal_extract_efuse_v2(mt, buf);
2381 + break;
2382 + case MTK_THERMAL_V3:
2383 + ret = mtk_thermal_extract_efuse_v3(mt, buf);
2384 + break;
2385 + default:
2386 + ret = -EINVAL;
2387 + break;
2388 + }
2389 +
2390 + if (ret) {
2391 + dev_info(dev, "Device not calibrated, using default calibration values\n");
2392 + ret = 0;
2393 + }
2394 +
2395 +out:
2396 + kfree(buf);
2397 +
2398 + return ret;
2399 +}
2400 +
2401 +static const struct of_device_id mtk_thermal_of_match[] = {
2402 + {
2403 + .compatible = "mediatek,mt8173-thermal",
2404 + .data = (void *)&mt8173_thermal_data,
2405 + },
2406 + {
2407 + .compatible = "mediatek,mt2701-thermal",
2408 + .data = (void *)&mt2701_thermal_data,
2409 + },
2410 + {
2411 + .compatible = "mediatek,mt2712-thermal",
2412 + .data = (void *)&mt2712_thermal_data,
2413 + },
2414 + {
2415 + .compatible = "mediatek,mt7622-thermal",
2416 + .data = (void *)&mt7622_thermal_data,
2417 + },
2418 + {
2419 + .compatible = "mediatek,mt7986-thermal",
2420 + .data = (void *)&mt7986_thermal_data,
2421 + },
2422 + {
2423 + .compatible = "mediatek,mt8183-thermal",
2424 + .data = (void *)&mt8183_thermal_data,
2425 + }, {
2426 + },
2427 +};
2428 +MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
2429 +
2430 +static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
2431 +{
2432 + int tmp;
2433 +
2434 + tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
2435 + tmp &= ~(0x37);
2436 + tmp |= 0x1;
2437 + writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
2438 + udelay(200);
2439 +}
2440 +
2441 +static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
2442 + void __iomem *auxadc_base)
2443 +{
2444 + int tmp;
2445 +
2446 + writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
2447 + writel(0x1, mt->thermal_base + TEMP_MONCTL0);
2448 + tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
2449 + writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
2450 +}
2451 +
2452 +static int mtk_thermal_probe(struct platform_device *pdev)
2453 +{
2454 + int ret, i, ctrl_id;
2455 + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
2456 + struct mtk_thermal *mt;
2457 + u64 auxadc_phys_base, apmixed_phys_base;
2458 + struct thermal_zone_device *tzdev;
2459 + void __iomem *apmixed_base, *auxadc_base;
2460 +
2461 + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
2462 + if (!mt)
2463 + return -ENOMEM;
2464 +
2465 + mt->conf = of_device_get_match_data(&pdev->dev);
2466 +
2467 + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
2468 + if (IS_ERR(mt->clk_peri_therm))
2469 + return PTR_ERR(mt->clk_peri_therm);
2470 +
2471 + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
2472 + if (IS_ERR(mt->clk_auxadc))
2473 + return PTR_ERR(mt->clk_auxadc);
2474 +
2475 + mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
2476 + if (IS_ERR(mt->thermal_base))
2477 + return PTR_ERR(mt->thermal_base);
2478 +
2479 + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
2480 + if (ret)
2481 + return ret;
2482 +
2483 + mutex_init(&mt->lock);
2484 +
2485 + mt->dev = &pdev->dev;
2486 +
2487 + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
2488 + if (!auxadc) {
2489 + dev_err(&pdev->dev, "missing auxadc node\n");
2490 + return -ENODEV;
2491 + }
2492 +
2493 + auxadc_base = of_iomap(auxadc, 0);
2494 + auxadc_phys_base = of_get_phys_base(auxadc);
2495 +
2496 + of_node_put(auxadc);
2497 +
2498 + if (auxadc_phys_base == OF_BAD_ADDR) {
2499 + dev_err(&pdev->dev, "Can't get auxadc phys address\n");
2500 + return -EINVAL;
2501 + }
2502 +
2503 + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
2504 + if (!apmixedsys) {
2505 + dev_err(&pdev->dev, "missing apmixedsys node\n");
2506 + return -ENODEV;
2507 + }
2508 +
2509 + apmixed_base = of_iomap(apmixedsys, 0);
2510 + apmixed_phys_base = of_get_phys_base(apmixedsys);
2511 +
2512 + of_node_put(apmixedsys);
2513 +
2514 + if (apmixed_phys_base == OF_BAD_ADDR) {
2515 + dev_err(&pdev->dev, "Can't get auxadc phys address\n");
2516 + return -EINVAL;
2517 + }
2518 +
2519 + ret = device_reset_optional(&pdev->dev);
2520 + if (ret)
2521 + return ret;
2522 +
2523 + ret = clk_prepare_enable(mt->clk_auxadc);
2524 + if (ret) {
2525 + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
2526 + return ret;
2527 + }
2528 +
2529 + ret = clk_prepare_enable(mt->clk_peri_therm);
2530 + if (ret) {
2531 + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
2532 + goto err_disable_clk_auxadc;
2533 + }
2534 +
2535 + if (mt->conf->version != MTK_THERMAL_V1) {
2536 + mtk_thermal_turn_on_buffer(apmixed_base);
2537 + mtk_thermal_release_periodic_ts(mt, auxadc_base);
2538 + }
2539 +
2540 + if (mt->conf->version == MTK_THERMAL_V1)
2541 + mt->raw_to_mcelsius = raw_to_mcelsius_v1;
2542 + else if (mt->conf->version == MTK_THERMAL_V2)
2543 + mt->raw_to_mcelsius = raw_to_mcelsius_v2;
2544 + else
2545 + mt->raw_to_mcelsius = raw_to_mcelsius_v3;
2546 +
2547 + for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
2548 + for (i = 0; i < mt->conf->num_banks; i++)
2549 + mtk_thermal_init_bank(mt, i, apmixed_phys_base,
2550 + auxadc_phys_base, ctrl_id);
2551 +
2552 + platform_set_drvdata(pdev, mt);
2553 +
2554 + tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
2555 + &mtk_thermal_ops);
2556 + if (IS_ERR(tzdev)) {
2557 + ret = PTR_ERR(tzdev);
2558 + goto err_disable_clk_peri_therm;
2559 + }
2560 +
2561 + ret = devm_thermal_add_hwmon_sysfs(tzdev);
2562 + if (ret)
2563 + dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
2564 +
2565 + return 0;
2566 +
2567 +err_disable_clk_peri_therm:
2568 + clk_disable_unprepare(mt->clk_peri_therm);
2569 +err_disable_clk_auxadc:
2570 + clk_disable_unprepare(mt->clk_auxadc);
2571 +
2572 + return ret;
2573 +}
2574 +
2575 +static int mtk_thermal_remove(struct platform_device *pdev)
2576 +{
2577 + struct mtk_thermal *mt = platform_get_drvdata(pdev);
2578 +
2579 + clk_disable_unprepare(mt->clk_peri_therm);
2580 + clk_disable_unprepare(mt->clk_auxadc);
2581 +
2582 + return 0;
2583 +}
2584 +
2585 +static struct platform_driver mtk_thermal_driver = {
2586 + .probe = mtk_thermal_probe,
2587 + .remove = mtk_thermal_remove,
2588 + .driver = {
2589 + .name = "mtk-thermal",
2590 + .of_match_table = mtk_thermal_of_match,
2591 + },
2592 +};
2593 +
2594 +module_platform_driver(mtk_thermal_driver);
2595 +
2596 +MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
2597 +MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
2598 +MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
2599 +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2600 +MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
2601 +MODULE_DESCRIPTION("Mediatek thermal driver");
2602 +MODULE_LICENSE("GPL v2");
Staging tree of Matthias Schiffer