1 From 723970affdd8766fa0d91cd34bf2ffc861538b5f Mon Sep 17 00:00:00 2001
2 From: Luo Jie <quic_luoj@quicinc.com>
3 Date: Sun, 16 Jul 2023 16:49:24 +0800
4 Subject: [PATCH 6/6] net: phy: at803x: add qca8081 fifo reset on the link
7 The qca8081 sgmii fifo needs to be reset on link down and
8 released on the link up in case of any abnormal issue
9 such as the packet blocked on the PHY.
11 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
12 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
13 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
14 Signed-off-by: David S. Miller <davem@davemloft.net>
16 drivers/net/phy/at803x.c | 14 ++++++++++++++
17 1 file changed, 14 insertions(+)
19 --- a/drivers/net/phy/at803x.c
20 +++ b/drivers/net/phy/at803x.c
22 #define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
23 #define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
25 +#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
26 +#define QCA8081_PHY_FIFO_RSTN BIT(11)
28 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
29 MODULE_AUTHOR("Matus Ujhelyi");
30 MODULE_LICENSE("GPL");
31 @@ -2037,6 +2040,16 @@ static int qca808x_get_features(struct p
35 +static void qca808x_link_change_notify(struct phy_device *phydev)
37 + /* Assert interface sgmii fifo on link down, deassert it on link up,
38 + * the interface device address is always phy address added by 1.
40 + mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
41 + MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
42 + QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
45 static struct phy_driver at803x_driver[] = {
47 /* Qualcomm Atheros AR8035 */
48 @@ -2213,6 +2226,7 @@ static struct phy_driver at803x_driver[]
49 .soft_reset = qca808x_soft_reset,
50 .cable_test_start = qca808x_cable_test_start,
51 .cable_test_get_status = qca808x_cable_test_get_status,
52 + .link_change_notify = qca808x_link_change_notify,
55 module_phy_driver(at803x_driver);