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[openwrt/staging/neocturne.git] /
1 From: Lorenzo Bianconi <lorenzo@kernel.org>
2 Date: Sat, 5 Nov 2022 23:36:21 +0100
3 Subject: [PATCH] net: ethernet: mtk_wed: add configure wed wo support
4
5 Enable RX Wireless Ethernet Dispatch available on MT7986 Soc.
6
7 Tested-by: Daniel Golle <daniel@makrotopia.org>
8 Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
9 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
10 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
11 Signed-off-by: David S. Miller <davem@davemloft.net>
12 ---
13
14 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
15 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
16 @@ -9,6 +9,7 @@
17 #include <linux/skbuff.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_address.h>
20 +#include <linux/of_reserved_mem.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/debugfs.h>
23 #include <linux/soc/mediatek/mtk_wed.h>
24 @@ -23,6 +24,7 @@
25 #define MTK_WED_PKT_SIZE 1900
26 #define MTK_WED_BUF_SIZE 2048
27 #define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048)
28 +#define MTK_WED_RX_RING_SIZE 1536
29
30 #define MTK_WED_TX_RING_SIZE 2048
31 #define MTK_WED_WDMA_RING_SIZE 1024
32 @@ -31,6 +33,10 @@
33 #define MTK_WED_PER_GROUP_PKT 128
34
35 #define MTK_WED_FBUF_SIZE 128
36 +#define MTK_WED_MIOD_CNT 16
37 +#define MTK_WED_FB_CMD_CNT 1024
38 +#define MTK_WED_RRO_QUE_CNT 8192
39 +#define MTK_WED_MIOD_ENTRY_CNT 128
40
41 static struct mtk_wed_hw *hw_list[2];
42 static DEFINE_MUTEX(hw_lock);
43 @@ -65,12 +71,76 @@ wdma_set(struct mtk_wed_device *dev, u32
44 wdma_m32(dev, reg, 0, mask);
45 }
46
47 +static void
48 +wdma_clr(struct mtk_wed_device *dev, u32 reg, u32 mask)
49 +{
50 + wdma_m32(dev, reg, mask, 0);
51 +}
52 +
53 +static u32
54 +wifi_r32(struct mtk_wed_device *dev, u32 reg)
55 +{
56 + return readl(dev->wlan.base + reg);
57 +}
58 +
59 +static void
60 +wifi_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
61 +{
62 + writel(val, dev->wlan.base + reg);
63 +}
64 +
65 static u32
66 mtk_wed_read_reset(struct mtk_wed_device *dev)
67 {
68 return wed_r32(dev, MTK_WED_RESET);
69 }
70
71 +static u32
72 +mtk_wdma_read_reset(struct mtk_wed_device *dev)
73 +{
74 + return wdma_r32(dev, MTK_WDMA_GLO_CFG);
75 +}
76 +
77 +static void
78 +mtk_wdma_rx_reset(struct mtk_wed_device *dev)
79 +{
80 + u32 status, mask = MTK_WDMA_GLO_CFG_RX_DMA_BUSY;
81 + int i;
82 +
83 + wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_DMA_EN);
84 + if (readx_poll_timeout(mtk_wdma_read_reset, dev, status,
85 + !(status & mask), 0, 1000))
86 + dev_err(dev->hw->dev, "rx reset failed\n");
87 +
88 + for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) {
89 + if (dev->rx_wdma[i].desc)
90 + continue;
91 +
92 + wdma_w32(dev,
93 + MTK_WDMA_RING_RX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);
94 + }
95 +}
96 +
97 +static void
98 +mtk_wdma_tx_reset(struct mtk_wed_device *dev)
99 +{
100 + u32 status, mask = MTK_WDMA_GLO_CFG_TX_DMA_BUSY;
101 + int i;
102 +
103 + wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
104 + if (readx_poll_timeout(mtk_wdma_read_reset, dev, status,
105 + !(status & mask), 0, 1000))
106 + dev_err(dev->hw->dev, "tx reset failed\n");
107 +
108 + for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) {
109 + if (dev->tx_wdma[i].desc)
110 + continue;
111 +
112 + wdma_w32(dev,
113 + MTK_WDMA_RING_TX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);
114 + }
115 +}
116 +
117 static void
118 mtk_wed_reset(struct mtk_wed_device *dev, u32 mask)
119 {
120 @@ -82,6 +152,54 @@ mtk_wed_reset(struct mtk_wed_device *dev
121 WARN_ON_ONCE(1);
122 }
123
124 +static u32
125 +mtk_wed_wo_read_status(struct mtk_wed_device *dev)
126 +{
127 + return wed_r32(dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_WO_STATUS);
128 +}
129 +
130 +static void
131 +mtk_wed_wo_reset(struct mtk_wed_device *dev)
132 +{
133 + struct mtk_wed_wo *wo = dev->hw->wed_wo;
134 + u8 state = MTK_WED_WO_STATE_DISABLE;
135 + void __iomem *reg;
136 + u32 val;
137 +
138 + mtk_wdma_tx_reset(dev);
139 + mtk_wed_reset(dev, MTK_WED_RESET_WED);
140 +
141 + mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
142 + MTK_WED_WO_CMD_CHANGE_STATE, &state,
143 + sizeof(state), false);
144 +
145 + if (readx_poll_timeout(mtk_wed_wo_read_status, dev, val,
146 + val == MTK_WED_WOIF_DISABLE_DONE,
147 + 100, MTK_WOCPU_TIMEOUT))
148 + dev_err(dev->hw->dev, "failed to disable wed-wo\n");
149 +
150 + reg = ioremap(MTK_WED_WO_CPU_MCUSYS_RESET_ADDR, 4);
151 +
152 + val = readl(reg);
153 + switch (dev->hw->index) {
154 + case 0:
155 + val |= MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK;
156 + writel(val, reg);
157 + val &= ~MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK;
158 + writel(val, reg);
159 + break;
160 + case 1:
161 + val |= MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK;
162 + writel(val, reg);
163 + val &= ~MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK;
164 + writel(val, reg);
165 + break;
166 + default:
167 + break;
168 + }
169 + iounmap(reg);
170 +}
171 +
172 static struct mtk_wed_hw *
173 mtk_wed_assign(struct mtk_wed_device *dev)
174 {
175 @@ -116,7 +234,7 @@ out:
176 }
177
178 static int
179 -mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
180 +mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
181 {
182 struct mtk_wdma_desc *desc;
183 dma_addr_t desc_phys;
184 @@ -133,16 +251,16 @@ mtk_wed_buffer_alloc(struct mtk_wed_devi
185 if (!page_list)
186 return -ENOMEM;
187
188 - dev->buf_ring.size = ring_size;
189 - dev->buf_ring.pages = page_list;
190 + dev->tx_buf_ring.size = ring_size;
191 + dev->tx_buf_ring.pages = page_list;
192
193 desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
194 &desc_phys, GFP_KERNEL);
195 if (!desc)
196 return -ENOMEM;
197
198 - dev->buf_ring.desc = desc;
199 - dev->buf_ring.desc_phys = desc_phys;
200 + dev->tx_buf_ring.desc = desc;
201 + dev->tx_buf_ring.desc_phys = desc_phys;
202
203 for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
204 dma_addr_t page_phys, buf_phys;
205 @@ -203,10 +321,10 @@ mtk_wed_buffer_alloc(struct mtk_wed_devi
206 }
207
208 static void
209 -mtk_wed_free_buffer(struct mtk_wed_device *dev)
210 +mtk_wed_free_tx_buffer(struct mtk_wed_device *dev)
211 {
212 - struct mtk_wdma_desc *desc = dev->buf_ring.desc;
213 - void **page_list = dev->buf_ring.pages;
214 + struct mtk_wdma_desc *desc = dev->tx_buf_ring.desc;
215 + void **page_list = dev->tx_buf_ring.pages;
216 int page_idx;
217 int i;
218
219 @@ -216,7 +334,8 @@ mtk_wed_free_buffer(struct mtk_wed_devic
220 if (!desc)
221 goto free_pagelist;
222
223 - for (i = 0, page_idx = 0; i < dev->buf_ring.size; i += MTK_WED_BUF_PER_PAGE) {
224 + for (i = 0, page_idx = 0; i < dev->tx_buf_ring.size;
225 + i += MTK_WED_BUF_PER_PAGE) {
226 void *page = page_list[page_idx++];
227 dma_addr_t buf_addr;
228
229 @@ -229,13 +348,59 @@ mtk_wed_free_buffer(struct mtk_wed_devic
230 __free_page(page);
231 }
232
233 - dma_free_coherent(dev->hw->dev, dev->buf_ring.size * sizeof(*desc),
234 - desc, dev->buf_ring.desc_phys);
235 + dma_free_coherent(dev->hw->dev, dev->tx_buf_ring.size * sizeof(*desc),
236 + desc, dev->tx_buf_ring.desc_phys);
237
238 free_pagelist:
239 kfree(page_list);
240 }
241
242 +static int
243 +mtk_wed_rx_buffer_alloc(struct mtk_wed_device *dev)
244 +{
245 + struct mtk_rxbm_desc *desc;
246 + dma_addr_t desc_phys;
247 +
248 + dev->rx_buf_ring.size = dev->wlan.rx_nbuf;
249 + desc = dma_alloc_coherent(dev->hw->dev,
250 + dev->wlan.rx_nbuf * sizeof(*desc),
251 + &desc_phys, GFP_KERNEL);
252 + if (!desc)
253 + return -ENOMEM;
254 +
255 + dev->rx_buf_ring.desc = desc;
256 + dev->rx_buf_ring.desc_phys = desc_phys;
257 + dev->wlan.init_rx_buf(dev, dev->wlan.rx_npkt);
258 +
259 + return 0;
260 +}
261 +
262 +static void
263 +mtk_wed_free_rx_buffer(struct mtk_wed_device *dev)
264 +{
265 + struct mtk_rxbm_desc *desc = dev->rx_buf_ring.desc;
266 +
267 + if (!desc)
268 + return;
269 +
270 + dev->wlan.release_rx_buf(dev);
271 + dma_free_coherent(dev->hw->dev, dev->rx_buf_ring.size * sizeof(*desc),
272 + desc, dev->rx_buf_ring.desc_phys);
273 +}
274 +
275 +static void
276 +mtk_wed_rx_buffer_hw_init(struct mtk_wed_device *dev)
277 +{
278 + wed_w32(dev, MTK_WED_RX_BM_RX_DMAD,
279 + FIELD_PREP(MTK_WED_RX_BM_RX_DMAD_SDL0, dev->wlan.rx_size));
280 + wed_w32(dev, MTK_WED_RX_BM_BASE, dev->rx_buf_ring.desc_phys);
281 + wed_w32(dev, MTK_WED_RX_BM_INIT_PTR, MTK_WED_RX_BM_INIT_SW_TAIL |
282 + FIELD_PREP(MTK_WED_RX_BM_SW_TAIL, dev->wlan.rx_npkt));
283 + wed_w32(dev, MTK_WED_RX_BM_DYN_ALLOC_TH,
284 + FIELD_PREP(MTK_WED_RX_BM_DYN_ALLOC_TH_H, 0xffff));
285 + wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
286 +}
287 +
288 static void
289 mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring)
290 {
291 @@ -247,6 +412,13 @@ mtk_wed_free_ring(struct mtk_wed_device
292 }
293
294 static void
295 +mtk_wed_free_rx_rings(struct mtk_wed_device *dev)
296 +{
297 + mtk_wed_free_rx_buffer(dev);
298 + mtk_wed_free_ring(dev, &dev->rro.ring);
299 +}
300 +
301 +static void
302 mtk_wed_free_tx_rings(struct mtk_wed_device *dev)
303 {
304 int i;
305 @@ -291,6 +463,38 @@ mtk_wed_set_512_support(struct mtk_wed_d
306 }
307 }
308
309 +#define MTK_WFMDA_RX_DMA_EN BIT(2)
310 +static void
311 +mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
312 +{
313 + u32 val;
314 + int i;
315 +
316 + if (!(dev->rx_ring[idx].flags & MTK_WED_RING_CONFIGURED))
317 + return; /* queue is not configured by mt76 */
318 +
319 + for (i = 0; i < 3; i++) {
320 + u32 cur_idx;
321 +
322 + cur_idx = wed_r32(dev,
323 + MTK_WED_WPDMA_RING_RX_DATA(idx) +
324 + MTK_WED_RING_OFS_CPU_IDX);
325 + if (cur_idx == MTK_WED_RX_RING_SIZE - 1)
326 + break;
327 +
328 + usleep_range(100000, 200000);
329 + }
330 +
331 + if (i == 3) {
332 + dev_err(dev->hw->dev, "rx dma enable failed\n");
333 + return;
334 + }
335 +
336 + val = wifi_r32(dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base) |
337 + MTK_WFMDA_RX_DMA_EN;
338 + wifi_w32(dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base, val);
339 +}
340 +
341 static void
342 mtk_wed_dma_disable(struct mtk_wed_device *dev)
343 {
344 @@ -304,20 +508,25 @@ mtk_wed_dma_disable(struct mtk_wed_devic
345 MTK_WED_GLO_CFG_TX_DMA_EN |
346 MTK_WED_GLO_CFG_RX_DMA_EN);
347
348 - wdma_m32(dev, MTK_WDMA_GLO_CFG,
349 + wdma_clr(dev, MTK_WDMA_GLO_CFG,
350 MTK_WDMA_GLO_CFG_TX_DMA_EN |
351 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
352 - MTK_WDMA_GLO_CFG_RX_INFO2_PRERES, 0);
353 + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
354
355 if (dev->hw->version == 1) {
356 regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
357 - wdma_m32(dev, MTK_WDMA_GLO_CFG,
358 - MTK_WDMA_GLO_CFG_RX_INFO3_PRERES, 0);
359 + wdma_clr(dev, MTK_WDMA_GLO_CFG,
360 + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
361 } else {
362 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
363 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
364 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
365
366 + wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
367 + MTK_WED_WPDMA_RX_D_RX_DRV_EN);
368 + wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
369 + MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
370 +
371 mtk_wed_set_512_support(dev, false);
372 }
373 }
374 @@ -338,6 +547,13 @@ mtk_wed_stop(struct mtk_wed_device *dev)
375 wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
376 wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
377 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
378 +
379 + if (dev->hw->version == 1)
380 + return;
381 +
382 + wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
383 + wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);
384 + wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
385 }
386
387 static void
388 @@ -353,11 +569,21 @@ mtk_wed_detach(struct mtk_wed_device *de
389 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
390
391 mtk_wed_reset(dev, MTK_WED_RESET_WED);
392 + if (mtk_wed_get_rx_capa(dev)) {
393 + wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
394 + wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
395 + wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
396 + }
397
398 - mtk_wed_free_buffer(dev);
399 + mtk_wed_free_tx_buffer(dev);
400 mtk_wed_free_tx_rings(dev);
401 - if (hw->version != 1)
402 +
403 + if (mtk_wed_get_rx_capa(dev)) {
404 + mtk_wed_wo_reset(dev);
405 + mtk_wed_free_rx_rings(dev);
406 mtk_wed_wo_deinit(hw);
407 + mtk_wdma_rx_reset(dev);
408 + }
409
410 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
411 struct device_node *wlan_node;
412 @@ -434,10 +660,12 @@ mtk_wed_set_wpdma(struct mtk_wed_device
413 } else {
414 mtk_wed_bus_init(dev);
415
416 - wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
417 - wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
418 - wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
419 - wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
420 + wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
421 + wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
422 + wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
423 + wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
424 + wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
425 + wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
426 }
427 }
428
429 @@ -487,6 +715,132 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
430 }
431 }
432
433 +static int
434 +mtk_wed_rro_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
435 + int size)
436 +{
437 + ring->desc = dma_alloc_coherent(dev->hw->dev,
438 + size * sizeof(*ring->desc),
439 + &ring->desc_phys, GFP_KERNEL);
440 + if (!ring->desc)
441 + return -ENOMEM;
442 +
443 + ring->desc_size = sizeof(*ring->desc);
444 + ring->size = size;
445 + memset(ring->desc, 0, size);
446 +
447 + return 0;
448 +}
449 +
450 +#define MTK_WED_MIOD_COUNT (MTK_WED_MIOD_ENTRY_CNT * MTK_WED_MIOD_CNT)
451 +static int
452 +mtk_wed_rro_alloc(struct mtk_wed_device *dev)
453 +{
454 + struct reserved_mem *rmem;
455 + struct device_node *np;
456 + int index;
457 +
458 + index = of_property_match_string(dev->hw->node, "memory-region-names",
459 + "wo-dlm");
460 + if (index < 0)
461 + return index;
462 +
463 + np = of_parse_phandle(dev->hw->node, "memory-region", index);
464 + if (!np)
465 + return -ENODEV;
466 +
467 + rmem = of_reserved_mem_lookup(np);
468 + of_node_put(np);
469 +
470 + if (!rmem)
471 + return -ENODEV;
472 +
473 + dev->rro.miod_phys = rmem->base;
474 + dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys;
475 +
476 + return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring,
477 + MTK_WED_RRO_QUE_CNT);
478 +}
479 +
480 +static int
481 +mtk_wed_rro_cfg(struct mtk_wed_device *dev)
482 +{
483 + struct mtk_wed_wo *wo = dev->hw->wed_wo;
484 + struct {
485 + struct {
486 + __le32 base;
487 + __le32 cnt;
488 + __le32 unit;
489 + } ring[2];
490 + __le32 wed;
491 + u8 version;
492 + } req = {
493 + .ring[0] = {
494 + .base = cpu_to_le32(MTK_WED_WOCPU_VIEW_MIOD_BASE),
495 + .cnt = cpu_to_le32(MTK_WED_MIOD_CNT),
496 + .unit = cpu_to_le32(MTK_WED_MIOD_ENTRY_CNT),
497 + },
498 + .ring[1] = {
499 + .base = cpu_to_le32(MTK_WED_WOCPU_VIEW_MIOD_BASE +
500 + MTK_WED_MIOD_COUNT),
501 + .cnt = cpu_to_le32(MTK_WED_FB_CMD_CNT),
502 + .unit = cpu_to_le32(4),
503 + },
504 + };
505 +
506 + return mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
507 + MTK_WED_WO_CMD_WED_CFG,
508 + &req, sizeof(req), true);
509 +}
510 +
511 +static void
512 +mtk_wed_rro_hw_init(struct mtk_wed_device *dev)
513 +{
514 + wed_w32(dev, MTK_WED_RROQM_MIOD_CFG,
515 + FIELD_PREP(MTK_WED_RROQM_MIOD_MID_DW, 0x70 >> 2) |
516 + FIELD_PREP(MTK_WED_RROQM_MIOD_MOD_DW, 0x10 >> 2) |
517 + FIELD_PREP(MTK_WED_RROQM_MIOD_ENTRY_DW,
518 + MTK_WED_MIOD_ENTRY_CNT >> 2));
519 +
520 + wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL0, dev->rro.miod_phys);
521 + wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL1,
522 + FIELD_PREP(MTK_WED_RROQM_MIOD_CNT, MTK_WED_MIOD_CNT));
523 + wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL0, dev->rro.fdbk_phys);
524 + wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL1,
525 + FIELD_PREP(MTK_WED_RROQM_FDBK_CNT, MTK_WED_FB_CMD_CNT));
526 + wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL2, 0);
527 + wed_w32(dev, MTK_WED_RROQ_BASE_L, dev->rro.ring.desc_phys);
528 +
529 + wed_set(dev, MTK_WED_RROQM_RST_IDX,
530 + MTK_WED_RROQM_RST_IDX_MIOD |
531 + MTK_WED_RROQM_RST_IDX_FDBK);
532 +
533 + wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
534 + wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL2, MTK_WED_MIOD_CNT - 1);
535 + wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN);
536 +}
537 +
538 +static void
539 +mtk_wed_route_qm_hw_init(struct mtk_wed_device *dev)
540 +{
541 + wed_w32(dev, MTK_WED_RESET, MTK_WED_RESET_RX_ROUTE_QM);
542 +
543 + for (;;) {
544 + usleep_range(100, 200);
545 + if (!(wed_r32(dev, MTK_WED_RESET) & MTK_WED_RESET_RX_ROUTE_QM))
546 + break;
547 + }
548 +
549 + /* configure RX_ROUTE_QM */
550 + wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
551 + wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
552 + wed_set(dev, MTK_WED_RTQM_GLO_CFG,
553 + FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT, 0x3 + dev->hw->index));
554 + wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
555 + /* enable RX_ROUTE_QM */
556 + wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
557 +}
558 +
559 static void
560 mtk_wed_hw_init(struct mtk_wed_device *dev)
561 {
562 @@ -498,11 +852,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
563 wed_w32(dev, MTK_WED_TX_BM_CTRL,
564 MTK_WED_TX_BM_CTRL_PAUSE |
565 FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
566 - dev->buf_ring.size / 128) |
567 + dev->tx_buf_ring.size / 128) |
568 FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
569 MTK_WED_TX_RING_SIZE / 256));
570
571 - wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys);
572 + wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys);
573
574 wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
575
576 @@ -529,9 +883,9 @@ mtk_wed_hw_init(struct mtk_wed_device *d
577 wed_w32(dev, MTK_WED_TX_TKID_CTRL,
578 MTK_WED_TX_TKID_CTRL_PAUSE |
579 FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM,
580 - dev->buf_ring.size / 128) |
581 + dev->tx_buf_ring.size / 128) |
582 FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
583 - dev->buf_ring.size / 128));
584 + dev->tx_buf_ring.size / 128));
585 wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
586 FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
587 MTK_WED_TX_TKID_DYN_THR_HI);
588 @@ -539,18 +893,28 @@ mtk_wed_hw_init(struct mtk_wed_device *d
589
590 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
591
592 - if (dev->hw->version == 1)
593 + if (dev->hw->version == 1) {
594 wed_set(dev, MTK_WED_CTRL,
595 MTK_WED_CTRL_WED_TX_BM_EN |
596 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
597 - else
598 + } else {
599 wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
600 + /* rx hw init */
601 + wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
602 + MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
603 + MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
604 + wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
605 +
606 + mtk_wed_rx_buffer_hw_init(dev);
607 + mtk_wed_rro_hw_init(dev);
608 + mtk_wed_route_qm_hw_init(dev);
609 + }
610
611 wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
612 }
613
614 static void
615 -mtk_wed_ring_reset(struct mtk_wed_ring *ring, int size)
616 +mtk_wed_ring_reset(struct mtk_wed_ring *ring, int size, bool tx)
617 {
618 void *head = (void *)ring->desc;
619 int i;
620 @@ -560,7 +924,10 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
621
622 desc = (struct mtk_wdma_desc *)(head + i * ring->desc_size);
623 desc->buf0 = 0;
624 - desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
625 + if (tx)
626 + desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
627 + else
628 + desc->ctrl = cpu_to_le32(MTK_WFDMA_DESC_CTRL_TO_HOST);
629 desc->buf1 = 0;
630 desc->info = 0;
631 }
632 @@ -616,7 +983,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
633 if (!dev->tx_ring[i].desc)
634 continue;
635
636 - mtk_wed_ring_reset(&dev->tx_ring[i], MTK_WED_TX_RING_SIZE);
637 + mtk_wed_ring_reset(&dev->tx_ring[i], MTK_WED_TX_RING_SIZE,
638 + true);
639 }
640
641 if (mtk_wed_poll_busy(dev))
642 @@ -634,6 +1002,9 @@ mtk_wed_reset_dma(struct mtk_wed_device
643 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
644 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
645
646 + if (mtk_wed_get_rx_capa(dev))
647 + mtk_wdma_rx_reset(dev);
648 +
649 if (busy) {
650 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
651 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);
652 @@ -668,12 +1039,11 @@ mtk_wed_reset_dma(struct mtk_wed_device
653 MTK_WED_WPDMA_RESET_IDX_RX);
654 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
655 }
656 -
657 }
658
659 static int
660 mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
661 - int size, u32 desc_size)
662 + int size, u32 desc_size, bool tx)
663 {
664 ring->desc = dma_alloc_coherent(dev->hw->dev, size * desc_size,
665 &ring->desc_phys, GFP_KERNEL);
666 @@ -682,7 +1052,7 @@ mtk_wed_ring_alloc(struct mtk_wed_device
667
668 ring->desc_size = desc_size;
669 ring->size = size;
670 - mtk_wed_ring_reset(ring, size);
671 + mtk_wed_ring_reset(ring, size, tx);
672
673 return 0;
674 }
675 @@ -691,9 +1061,14 @@ static int
676 mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
677 {
678 u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
679 - struct mtk_wed_ring *wdma = &dev->rx_wdma[idx];
680 + struct mtk_wed_ring *wdma;
681
682 - if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, desc_size))
683 + if (idx >= ARRAY_SIZE(dev->rx_wdma))
684 + return -EINVAL;
685 +
686 + wdma = &dev->rx_wdma[idx];
687 + if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, desc_size,
688 + true))
689 return -ENOMEM;
690
691 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
692 @@ -710,6 +1085,60 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
693 return 0;
694 }
695
696 +static int
697 +mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
698 +{
699 + u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
700 + struct mtk_wed_ring *wdma;
701 +
702 + if (idx >= ARRAY_SIZE(dev->tx_wdma))
703 + return -EINVAL;
704 +
705 + wdma = &dev->tx_wdma[idx];
706 + if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, desc_size,
707 + true))
708 + return -ENOMEM;
709 +
710 + wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
711 + wdma->desc_phys);
712 + wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
713 + size);
714 + wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
715 + wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);
716 +
717 + if (!idx) {
718 + wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_BASE,
719 + wdma->desc_phys);
720 + wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_COUNT,
721 + size);
722 + wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_CPU_IDX,
723 + 0);
724 + wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_DMA_IDX,
725 + 0);
726 + }
727 +
728 + return 0;
729 +}
730 +
731 +static void
732 +mtk_wed_ppe_check(struct mtk_wed_device *dev, struct sk_buff *skb,
733 + u32 reason, u32 hash)
734 +{
735 + struct mtk_eth *eth = dev->hw->eth;
736 + struct ethhdr *eh;
737 +
738 + if (!skb)
739 + return;
740 +
741 + if (reason != MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
742 + return;
743 +
744 + skb_set_mac_header(skb, 0);
745 + eh = eth_hdr(skb);
746 + skb->protocol = eh->h_proto;
747 + mtk_ppe_check_skb(eth->ppe[dev->hw->index], skb, hash);
748 +}
749 +
750 static void
751 mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
752 {
753 @@ -732,6 +1161,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
754
755 wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
756 } else {
757 + wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
758 + GENMASK(1, 0));
759 /* initail tx interrupt trigger */
760 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
761 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
762 @@ -750,6 +1181,16 @@ mtk_wed_configure_irq(struct mtk_wed_dev
763 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
764 dev->wlan.txfree_tbit));
765
766 + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
767 + MTK_WED_WPDMA_INT_CTRL_RX0_EN |
768 + MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
769 + MTK_WED_WPDMA_INT_CTRL_RX1_EN |
770 + MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
771 + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
772 + dev->wlan.rx_tbit[0]) |
773 + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
774 + dev->wlan.rx_tbit[1]));
775 +
776 wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
777 wed_set(dev, MTK_WED_WDMA_INT_CTRL,
778 FIELD_PREP(MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL,
779 @@ -787,9 +1228,15 @@ mtk_wed_dma_enable(struct mtk_wed_device
780 wdma_set(dev, MTK_WDMA_GLO_CFG,
781 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
782 } else {
783 + int i;
784 +
785 wed_set(dev, MTK_WED_WPDMA_CTRL,
786 MTK_WED_WPDMA_CTRL_SDL1_FIXED);
787
788 + wed_set(dev, MTK_WED_WDMA_GLO_CFG,
789 + MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
790 + MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
791 +
792 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
793 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
794 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
795 @@ -797,6 +1244,15 @@ mtk_wed_dma_enable(struct mtk_wed_device
796 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
797 MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
798 MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
799 +
800 + wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
801 + MTK_WED_WPDMA_RX_D_RX_DRV_EN |
802 + FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
803 + FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
804 + 0x2));
805 +
806 + for (i = 0; i < MTK_WED_RX_QUEUES; i++)
807 + mtk_wed_check_wfdma_rx_fill(dev, i);
808 }
809 }
810
811 @@ -822,7 +1278,19 @@ mtk_wed_start(struct mtk_wed_device *dev
812 val |= BIT(0) | (BIT(1) * !!dev->hw->index);
813 regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
814 } else {
815 - mtk_wed_set_512_support(dev, true);
816 + /* driver set mid ready and only once */
817 + wed_w32(dev, MTK_WED_EXT_INT_MASK1,
818 + MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
819 + wed_w32(dev, MTK_WED_EXT_INT_MASK2,
820 + MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
821 +
822 + wed_r32(dev, MTK_WED_EXT_INT_MASK1);
823 + wed_r32(dev, MTK_WED_EXT_INT_MASK2);
824 +
825 + if (mtk_wed_rro_cfg(dev))
826 + return;
827 +
828 + mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
829 }
830
831 mtk_wed_dma_enable(dev);
832 @@ -856,7 +1324,7 @@ mtk_wed_attach(struct mtk_wed_device *de
833 if (!hw) {
834 module_put(THIS_MODULE);
835 ret = -ENODEV;
836 - goto out;
837 + goto unlock;
838 }
839
840 device = dev->wlan.bus_type == MTK_WED_BUS_PCIE
841 @@ -869,15 +1337,24 @@ mtk_wed_attach(struct mtk_wed_device *de
842 dev->dev = hw->dev;
843 dev->irq = hw->irq;
844 dev->wdma_idx = hw->index;
845 + dev->version = hw->version;
846
847 if (hw->eth->dma_dev == hw->eth->dev &&
848 of_dma_is_coherent(hw->eth->dev->of_node))
849 mtk_eth_set_dma_device(hw->eth, hw->dev);
850
851 - ret = mtk_wed_buffer_alloc(dev);
852 - if (ret) {
853 - mtk_wed_detach(dev);
854 + ret = mtk_wed_tx_buffer_alloc(dev);
855 + if (ret)
856 goto out;
857 +
858 + if (mtk_wed_get_rx_capa(dev)) {
859 + ret = mtk_wed_rx_buffer_alloc(dev);
860 + if (ret)
861 + goto out;
862 +
863 + ret = mtk_wed_rro_alloc(dev);
864 + if (ret)
865 + goto out;
866 }
867
868 mtk_wed_hw_init_early(dev);
869 @@ -886,8 +1363,10 @@ mtk_wed_attach(struct mtk_wed_device *de
870 BIT(hw->index), 0);
871 else
872 ret = mtk_wed_wo_init(hw);
873 -
874 out:
875 + if (ret)
876 + mtk_wed_detach(dev);
877 +unlock:
878 mutex_unlock(&hw_lock);
879
880 return ret;
881 @@ -910,10 +1389,11 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
882 * WDMA RX.
883 */
884
885 - BUG_ON(idx >= ARRAY_SIZE(dev->tx_ring));
886 + if (WARN_ON(idx >= ARRAY_SIZE(dev->tx_ring)))
887 + return -EINVAL;
888
889 if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE,
890 - sizeof(*ring->desc)))
891 + sizeof(*ring->desc), true))
892 return -ENOMEM;
893
894 if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
895 @@ -960,6 +1440,37 @@ mtk_wed_txfree_ring_setup(struct mtk_wed
896 return 0;
897 }
898
899 +static int
900 +mtk_wed_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
901 +{
902 + struct mtk_wed_ring *ring = &dev->rx_ring[idx];
903 +
904 + if (WARN_ON(idx >= ARRAY_SIZE(dev->rx_ring)))
905 + return -EINVAL;
906 +
907 + if (mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE,
908 + sizeof(*ring->desc), false))
909 + return -ENOMEM;
910 +
911 + if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
912 + return -ENOMEM;
913 +
914 + ring->reg_base = MTK_WED_RING_RX_DATA(idx);
915 + ring->wpdma = regs;
916 + ring->flags |= MTK_WED_RING_CONFIGURED;
917 +
918 + /* WPDMA -> WED */
919 + wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
920 + wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_RX_RING_SIZE);
921 +
922 + wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_BASE,
923 + ring->desc_phys);
924 + wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_COUNT,
925 + MTK_WED_RX_RING_SIZE);
926 +
927 + return 0;
928 +}
929 +
930 static u32
931 mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
932 {
933 @@ -1056,7 +1567,9 @@ void mtk_wed_add_hw(struct device_node *
934 static const struct mtk_wed_ops wed_ops = {
935 .attach = mtk_wed_attach,
936 .tx_ring_setup = mtk_wed_tx_ring_setup,
937 + .rx_ring_setup = mtk_wed_rx_ring_setup,
938 .txfree_ring_setup = mtk_wed_txfree_ring_setup,
939 + .msg_update = mtk_wed_mcu_msg_update,
940 .start = mtk_wed_start,
941 .stop = mtk_wed_stop,
942 .reset_dma = mtk_wed_reset_dma,
943 @@ -1065,6 +1578,7 @@ void mtk_wed_add_hw(struct device_node *
944 .irq_get = mtk_wed_irq_get,
945 .irq_set_mask = mtk_wed_irq_set_mask,
946 .detach = mtk_wed_detach,
947 + .ppe_check = mtk_wed_ppe_check,
948 };
949 struct device_node *eth_np = eth->dev->of_node;
950 struct platform_device *pdev;
951 --- a/drivers/net/ethernet/mediatek/mtk_wed.h
952 +++ b/drivers/net/ethernet/mediatek/mtk_wed.h
953 @@ -87,6 +87,24 @@ wpdma_tx_w32(struct mtk_wed_device *dev,
954 }
955
956 static inline u32
957 +wpdma_rx_r32(struct mtk_wed_device *dev, int ring, u32 reg)
958 +{
959 + if (!dev->rx_ring[ring].wpdma)
960 + return 0;
961 +
962 + return readl(dev->rx_ring[ring].wpdma + reg);
963 +}
964 +
965 +static inline void
966 +wpdma_rx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)
967 +{
968 + if (!dev->rx_ring[ring].wpdma)
969 + return;
970 +
971 + writel(val, dev->rx_ring[ring].wpdma + reg);
972 +}
973 +
974 +static inline u32
975 wpdma_txfree_r32(struct mtk_wed_device *dev, u32 reg)
976 {
977 if (!dev->txfree_ring.wpdma)
978 @@ -128,6 +146,7 @@ static inline int mtk_wed_flow_add(int i
979 static inline void mtk_wed_flow_remove(int index)
980 {
981 }
982 +
983 #endif
984
985 #ifdef CONFIG_DEBUG_FS
986 --- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
987 +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
988 @@ -10,6 +10,7 @@
989 #include <linux/of_reserved_mem.h>
990 #include <linux/mfd/syscon.h>
991 #include <linux/soc/mediatek/mtk_wed.h>
992 +#include <asm/unaligned.h>
993
994 #include "mtk_wed_regs.h"
995 #include "mtk_wed_wo.h"
996 @@ -60,24 +61,37 @@ void mtk_wed_mcu_rx_event(struct mtk_wed
997 wake_up(&wo->mcu.wait);
998 }
999
1000 +static void
1001 +mtk_wed_update_rx_stats(struct mtk_wed_device *wed, struct sk_buff *skb)
1002 +{
1003 + u32 count = get_unaligned_le32(skb->data);
1004 + struct mtk_wed_wo_rx_stats *stats;
1005 + int i;
1006 +
1007 + if (count * sizeof(*stats) > skb->len - sizeof(u32))
1008 + return;
1009 +
1010 + stats = (struct mtk_wed_wo_rx_stats *)(skb->data + sizeof(u32));
1011 + for (i = 0 ; i < count ; i++)
1012 + wed->wlan.update_wo_rx_stats(wed, &stats[i]);
1013 +}
1014 +
1015 void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
1016 struct sk_buff *skb)
1017 {
1018 struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
1019
1020 - switch (hdr->cmd) {
1021 - case MTK_WED_WO_EVT_LOG_DUMP: {
1022 - const char *msg = (const char *)(skb->data + sizeof(*hdr));
1023 + skb_pull(skb, sizeof(*hdr));
1024
1025 - dev_notice(wo->hw->dev, "%s\n", msg);
1026 + switch (hdr->cmd) {
1027 + case MTK_WED_WO_EVT_LOG_DUMP:
1028 + dev_notice(wo->hw->dev, "%s\n", skb->data);
1029 break;
1030 - }
1031 case MTK_WED_WO_EVT_PROFILING: {
1032 - struct mtk_wed_wo_log_info *info;
1033 - u32 count = (skb->len - sizeof(*hdr)) / sizeof(*info);
1034 + struct mtk_wed_wo_log_info *info = (void *)skb->data;
1035 + u32 count = skb->len / sizeof(*info);
1036 int i;
1037
1038 - info = (struct mtk_wed_wo_log_info *)(skb->data + sizeof(*hdr));
1039 for (i = 0 ; i < count ; i++)
1040 dev_notice(wo->hw->dev,
1041 "SN:%u latency: total=%u, rro:%u, mod:%u\n",
1042 @@ -88,6 +102,7 @@ void mtk_wed_mcu_rx_unsolicited_event(st
1043 break;
1044 }
1045 case MTK_WED_WO_EVT_RXCNT_INFO:
1046 + mtk_wed_update_rx_stats(wo->hw->wed_dev, skb);
1047 break;
1048 default:
1049 break;
1050 @@ -144,6 +159,8 @@ mtk_wed_mcu_parse_response(struct mtk_we
1051 skb_pull(skb, sizeof(*hdr));
1052 switch (cmd) {
1053 case MTK_WED_WO_CMD_RXCNT_INFO:
1054 + mtk_wed_update_rx_stats(wo->hw->wed_dev, skb);
1055 + break;
1056 default:
1057 break;
1058 }
1059 @@ -182,6 +199,18 @@ unlock:
1060 return ret;
1061 }
1062
1063 +int mtk_wed_mcu_msg_update(struct mtk_wed_device *dev, int id, void *data,
1064 + int len)
1065 +{
1066 + struct mtk_wed_wo *wo = dev->hw->wed_wo;
1067 +
1068 + if (dev->hw->version == 1)
1069 + return 0;
1070 +
1071 + return mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO, id, data, len,
1072 + true);
1073 +}
1074 +
1075 static int
1076 mtk_wed_get_memory_region(struct mtk_wed_wo *wo,
1077 struct mtk_wed_wo_memory_region *region)
1078 --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
1079 +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
1080 @@ -4,6 +4,7 @@
1081 #ifndef __MTK_WED_REGS_H
1082 #define __MTK_WED_REGS_H
1083
1084 +#define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)
1085 #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
1086 #define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)
1087 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
1088 @@ -28,6 +29,8 @@ struct mtk_wdma_desc {
1089 #define MTK_WED_RESET_WED_TX_DMA BIT(12)
1090 #define MTK_WED_RESET_WDMA_RX_DRV BIT(17)
1091 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
1092 +#define MTK_WED_RESET_RX_RRO_QM BIT(20)
1093 +#define MTK_WED_RESET_RX_ROUTE_QM BIT(21)
1094 #define MTK_WED_RESET_WED BIT(31)
1095
1096 #define MTK_WED_CTRL 0x00c
1097 @@ -39,8 +42,12 @@ struct mtk_wdma_desc {
1098 #define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)
1099 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)
1100 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11)
1101 -#define MTK_WED_CTRL_RESERVE_EN BIT(12)
1102 -#define MTK_WED_CTRL_RESERVE_BUSY BIT(13)
1103 +#define MTK_WED_CTRL_WED_RX_BM_EN BIT(12)
1104 +#define MTK_WED_CTRL_WED_RX_BM_BUSY BIT(13)
1105 +#define MTK_WED_CTRL_RX_RRO_QM_EN BIT(14)
1106 +#define MTK_WED_CTRL_RX_RRO_QM_BUSY BIT(15)
1107 +#define MTK_WED_CTRL_RX_ROUTE_QM_EN BIT(16)
1108 +#define MTK_WED_CTRL_RX_ROUTE_QM_BUSY BIT(17)
1109 #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
1110 #define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)
1111 #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
1112 @@ -62,6 +69,9 @@ struct mtk_wdma_desc {
1113 #define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22)
1114 #define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23)
1115 #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24)
1116 +#define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25)
1117 +#define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26)
1118 +#define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27)
1119 #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \
1120 MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \
1121 MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \
1122 @@ -71,6 +81,8 @@ struct mtk_wdma_desc {
1123 MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR)
1124
1125 #define MTK_WED_EXT_INT_MASK 0x028
1126 +#define MTK_WED_EXT_INT_MASK1 0x02c
1127 +#define MTK_WED_EXT_INT_MASK2 0x030
1128
1129 #define MTK_WED_STATUS 0x060
1130 #define MTK_WED_STATUS_TX GENMASK(15, 8)
1131 @@ -151,6 +163,7 @@ struct mtk_wdma_desc {
1132 #define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10)
1133
1134 #define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10)
1135 +#define MTK_WED_RING_RX_DATA(_n) (0x420 + (_n) * 0x10)
1136
1137 #define MTK_WED_SCR0 0x3c0
1138 #define MTK_WED_WPDMA_INT_TRIGGER 0x504
1139 @@ -213,6 +226,12 @@ struct mtk_wdma_desc {
1140 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10)
1141
1142 #define MTK_WED_WPDMA_INT_CTRL_RX 0x534
1143 +#define MTK_WED_WPDMA_INT_CTRL_RX0_EN BIT(0)
1144 +#define MTK_WED_WPDMA_INT_CTRL_RX0_CLR BIT(1)
1145 +#define MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG GENMASK(6, 2)
1146 +#define MTK_WED_WPDMA_INT_CTRL_RX1_EN BIT(8)
1147 +#define MTK_WED_WPDMA_INT_CTRL_RX1_CLR BIT(9)
1148 +#define MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG GENMASK(14, 10)
1149
1150 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538
1151 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0)
1152 @@ -242,11 +261,34 @@ struct mtk_wdma_desc {
1153
1154 #define MTK_WED_WPDMA_RING_TX(_n) (0x600 + (_n) * 0x10)
1155 #define MTK_WED_WPDMA_RING_RX(_n) (0x700 + (_n) * 0x10)
1156 +#define MTK_WED_WPDMA_RING_RX_DATA(_n) (0x730 + (_n) * 0x10)
1157 +
1158 +#define MTK_WED_WPDMA_RX_D_GLO_CFG 0x75c
1159 +#define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0)
1160 +#define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL GENMASK(11, 7)
1161 +#define MTK_WED_WPDMA_RX_D_RXD_READ_LEN GENMASK(31, 24)
1162 +
1163 +#define MTK_WED_WPDMA_RX_D_RST_IDX 0x760
1164 +#define MTK_WED_WPDMA_RX_D_RST_CRX_IDX GENMASK(17, 16)
1165 +#define MTK_WED_WPDMA_RX_D_RST_DRV_IDX GENMASK(25, 24)
1166 +
1167 +#define MTK_WED_WPDMA_RX_GLO_CFG 0x76c
1168 +#define MTK_WED_WPDMA_RX_RING 0x770
1169 +
1170 +#define MTK_WED_WPDMA_RX_D_MIB(_n) (0x774 + (_n) * 4)
1171 +#define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n) (0x784 + (_n) * 4)
1172 +#define MTK_WED_WPDMA_RX_D_COHERENT_MIB 0x78c
1173 +
1174 +#define MTK_WED_WDMA_RING_TX 0x800
1175 +
1176 +#define MTK_WED_WDMA_TX_MIB 0x810
1177 +
1178 #define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10)
1179 #define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4)
1180
1181 #define MTK_WED_WDMA_GLO_CFG 0xa04
1182 #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
1183 +#define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK BIT(1)
1184 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2)
1185 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
1186 #define MTK_WED_WDMA_GLO_CFG_BT_SIZE GENMASK(5, 4)
1187 @@ -291,6 +333,20 @@ struct mtk_wdma_desc {
1188 #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4)
1189 #define MTK_WED_WDMA_RX_PROCESSED_MIB(_n) (0xaf0 + (_n) * 4)
1190
1191 +#define MTK_WED_RX_BM_RX_DMAD 0xd80
1192 +#define MTK_WED_RX_BM_RX_DMAD_SDL0 GENMASK(13, 0)
1193 +
1194 +#define MTK_WED_RX_BM_BASE 0xd84
1195 +#define MTK_WED_RX_BM_INIT_PTR 0xd88
1196 +#define MTK_WED_RX_BM_SW_TAIL GENMASK(15, 0)
1197 +#define MTK_WED_RX_BM_INIT_SW_TAIL BIT(16)
1198 +
1199 +#define MTK_WED_RX_PTR 0xd8c
1200 +
1201 +#define MTK_WED_RX_BM_DYN_ALLOC_TH 0xdb4
1202 +#define MTK_WED_RX_BM_DYN_ALLOC_TH_H GENMASK(31, 16)
1203 +#define MTK_WED_RX_BM_DYN_ALLOC_TH_L GENMASK(15, 0)
1204 +
1205 #define MTK_WED_RING_OFS_BASE 0x00
1206 #define MTK_WED_RING_OFS_COUNT 0x04
1207 #define MTK_WED_RING_OFS_CPU_IDX 0x08
1208 @@ -301,7 +357,9 @@ struct mtk_wdma_desc {
1209
1210 #define MTK_WDMA_GLO_CFG 0x204
1211 #define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)
1212 +#define MTK_WDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
1213 #define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2)
1214 +#define MTK_WDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
1215 #define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26)
1216 #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
1217 #define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28)
1218 @@ -330,4 +388,70 @@ struct mtk_wdma_desc {
1219 /* DMA channel mapping */
1220 #define HIFSYS_DMA_AG_MAP 0x008
1221
1222 +#define MTK_WED_RTQM_GLO_CFG 0xb00
1223 +#define MTK_WED_RTQM_BUSY BIT(1)
1224 +#define MTK_WED_RTQM_Q_RST BIT(2)
1225 +#define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5)
1226 +#define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20)
1227 +
1228 +#define MTK_WED_RTQM_R2H_MIB(_n) (0xb70 + (_n) * 0x4)
1229 +#define MTK_WED_RTQM_R2Q_MIB(_n) (0xb78 + (_n) * 0x4)
1230 +#define MTK_WED_RTQM_Q2N_MIB 0xb80
1231 +#define MTK_WED_RTQM_Q2H_MIB(_n) (0xb84 + (_n) * 0x4)
1232 +
1233 +#define MTK_WED_RTQM_Q2B_MIB 0xb8c
1234 +#define MTK_WED_RTQM_PFDBK_MIB 0xb90
1235 +
1236 +#define MTK_WED_RROQM_GLO_CFG 0xc04
1237 +#define MTK_WED_RROQM_RST_IDX 0xc08
1238 +#define MTK_WED_RROQM_RST_IDX_MIOD BIT(0)
1239 +#define MTK_WED_RROQM_RST_IDX_FDBK BIT(4)
1240 +
1241 +#define MTK_WED_RROQM_MIOD_CTRL0 0xc40
1242 +#define MTK_WED_RROQM_MIOD_CTRL1 0xc44
1243 +#define MTK_WED_RROQM_MIOD_CNT GENMASK(11, 0)
1244 +
1245 +#define MTK_WED_RROQM_MIOD_CTRL2 0xc48
1246 +#define MTK_WED_RROQM_MIOD_CTRL3 0xc4c
1247 +
1248 +#define MTK_WED_RROQM_FDBK_CTRL0 0xc50
1249 +#define MTK_WED_RROQM_FDBK_CTRL1 0xc54
1250 +#define MTK_WED_RROQM_FDBK_CNT GENMASK(11, 0)
1251 +
1252 +#define MTK_WED_RROQM_FDBK_CTRL2 0xc58
1253 +
1254 +#define MTK_WED_RROQ_BASE_L 0xc80
1255 +#define MTK_WED_RROQ_BASE_H 0xc84
1256 +
1257 +#define MTK_WED_RROQM_MIOD_CFG 0xc8c
1258 +#define MTK_WED_RROQM_MIOD_MID_DW GENMASK(5, 0)
1259 +#define MTK_WED_RROQM_MIOD_MOD_DW GENMASK(13, 8)
1260 +#define MTK_WED_RROQM_MIOD_ENTRY_DW GENMASK(22, 16)
1261 +
1262 +#define MTK_WED_RROQM_MID_MIB 0xcc0
1263 +#define MTK_WED_RROQM_MOD_MIB 0xcc4
1264 +#define MTK_WED_RROQM_MOD_COHERENT_MIB 0xcc8
1265 +#define MTK_WED_RROQM_FDBK_MIB 0xcd0
1266 +#define MTK_WED_RROQM_FDBK_COHERENT_MIB 0xcd4
1267 +#define MTK_WED_RROQM_FDBK_IND_MIB 0xce0
1268 +#define MTK_WED_RROQM_FDBK_ENQ_MIB 0xce4
1269 +#define MTK_WED_RROQM_FDBK_ANC_MIB 0xce8
1270 +#define MTK_WED_RROQM_FDBK_ANC2H_MIB 0xcec
1271 +
1272 +#define MTK_WED_RX_BM_RX_DMAD 0xd80
1273 +#define MTK_WED_RX_BM_BASE 0xd84
1274 +#define MTK_WED_RX_BM_INIT_PTR 0xd88
1275 +#define MTK_WED_RX_BM_PTR 0xd8c
1276 +#define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)
1277 +#define MTK_WED_RX_BM_PTR_TAIL GENMASK(15, 0)
1278 +
1279 +#define MTK_WED_RX_BM_BLEN 0xd90
1280 +#define MTK_WED_RX_BM_STS 0xd94
1281 +#define MTK_WED_RX_BM_INTF2 0xd98
1282 +#define MTK_WED_RX_BM_INTF 0xd9c
1283 +#define MTK_WED_RX_BM_ERR_STS 0xda8
1284 +
1285 +#define MTK_WED_WOCPU_VIEW_MIOD_BASE 0x8000
1286 +#define MTK_WED_PCIE_INT_MASK 0x0
1287 +
1288 #endif
1289 --- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
1290 +++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
1291 @@ -49,6 +49,10 @@ enum {
1292 MTK_WED_WARP_CMD_FLAG_FROM_TO_WO = BIT(2),
1293 };
1294
1295 +#define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR 0x15194050
1296 +#define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK 0x20
1297 +#define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK 0x1
1298 +
1299 enum {
1300 MTK_WED_WO_REGION_EMI,
1301 MTK_WED_WO_REGION_ILM,
1302 @@ -57,6 +61,28 @@ enum {
1303 __MTK_WED_WO_REGION_MAX,
1304 };
1305
1306 +enum mtk_wed_wo_state {
1307 + MTK_WED_WO_STATE_UNDEFINED,
1308 + MTK_WED_WO_STATE_INIT,
1309 + MTK_WED_WO_STATE_ENABLE,
1310 + MTK_WED_WO_STATE_DISABLE,
1311 + MTK_WED_WO_STATE_HALT,
1312 + MTK_WED_WO_STATE_GATING,
1313 + MTK_WED_WO_STATE_SER_RESET,
1314 + MTK_WED_WO_STATE_WF_RESET,
1315 +};
1316 +
1317 +enum mtk_wed_wo_done_state {
1318 + MTK_WED_WOIF_UNDEFINED,
1319 + MTK_WED_WOIF_DISABLE_DONE,
1320 + MTK_WED_WOIF_TRIGGER_ENABLE,
1321 + MTK_WED_WOIF_ENABLE_DONE,
1322 + MTK_WED_WOIF_TRIGGER_GATING,
1323 + MTK_WED_WOIF_GATING_DONE,
1324 + MTK_WED_WOIF_TRIGGER_HALT,
1325 + MTK_WED_WOIF_HALT_DONE,
1326 +};
1327 +
1328 enum mtk_wed_dummy_cr_idx {
1329 MTK_WED_DUMMY_CR_FWDL,
1330 MTK_WED_DUMMY_CR_WO_STATUS,
1331 @@ -245,6 +271,8 @@ void mtk_wed_mcu_rx_unsolicited_event(st
1332 struct sk_buff *skb);
1333 int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
1334 const void *data, int len, bool wait_resp);
1335 +int mtk_wed_mcu_msg_update(struct mtk_wed_device *dev, int id, void *data,
1336 + int len);
1337 int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
1338 int mtk_wed_wo_init(struct mtk_wed_hw *hw);
1339 void mtk_wed_wo_deinit(struct mtk_wed_hw *hw);
1340 --- a/include/linux/soc/mediatek/mtk_wed.h
1341 +++ b/include/linux/soc/mediatek/mtk_wed.h
1342 @@ -5,10 +5,13 @@
1343 #include <linux/rcupdate.h>
1344 #include <linux/regmap.h>
1345 #include <linux/pci.h>
1346 +#include <linux/skbuff.h>
1347
1348 #define MTK_WED_TX_QUEUES 2
1349 #define MTK_WED_RX_QUEUES 2
1350
1351 +#define WED_WO_STA_REC 0x6
1352 +
1353 struct mtk_wed_hw;
1354 struct mtk_wdma_desc;
1355
1356 @@ -41,21 +44,37 @@ enum mtk_wed_wo_cmd {
1357 MTK_WED_WO_CMD_WED_END
1358 };
1359
1360 +struct mtk_rxbm_desc {
1361 + __le32 buf0;
1362 + __le32 token;
1363 +} __packed __aligned(4);
1364 +
1365 enum mtk_wed_bus_tye {
1366 MTK_WED_BUS_PCIE,
1367 MTK_WED_BUS_AXI,
1368 };
1369
1370 +#define MTK_WED_RING_CONFIGURED BIT(0)
1371 struct mtk_wed_ring {
1372 struct mtk_wdma_desc *desc;
1373 dma_addr_t desc_phys;
1374 u32 desc_size;
1375 int size;
1376 + u32 flags;
1377
1378 u32 reg_base;
1379 void __iomem *wpdma;
1380 };
1381
1382 +struct mtk_wed_wo_rx_stats {
1383 + __le16 wlan_idx;
1384 + __le16 tid;
1385 + __le32 rx_pkt_cnt;
1386 + __le32 rx_byte_cnt;
1387 + __le32 rx_err_cnt;
1388 + __le32 rx_drop_cnt;
1389 +};
1390 +
1391 struct mtk_wed_device {
1392 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
1393 const struct mtk_wed_ops *ops;
1394 @@ -64,9 +83,12 @@ struct mtk_wed_device {
1395 bool init_done, running;
1396 int wdma_idx;
1397 int irq;
1398 + u8 version;
1399
1400 struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES];
1401 + struct mtk_wed_ring rx_ring[MTK_WED_RX_QUEUES];
1402 struct mtk_wed_ring txfree_ring;
1403 + struct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES];
1404 struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES];
1405
1406 struct {
1407 @@ -74,7 +96,20 @@ struct mtk_wed_device {
1408 void **pages;
1409 struct mtk_wdma_desc *desc;
1410 dma_addr_t desc_phys;
1411 - } buf_ring;
1412 + } tx_buf_ring;
1413 +
1414 + struct {
1415 + int size;
1416 + struct page_frag_cache rx_page;
1417 + struct mtk_rxbm_desc *desc;
1418 + dma_addr_t desc_phys;
1419 + } rx_buf_ring;
1420 +
1421 + struct {
1422 + struct mtk_wed_ring ring;
1423 + dma_addr_t miod_phys;
1424 + dma_addr_t fdbk_phys;
1425 + } rro;
1426
1427 /* filled by driver: */
1428 struct {
1429 @@ -83,22 +118,36 @@ struct mtk_wed_device {
1430 struct pci_dev *pci_dev;
1431 };
1432 enum mtk_wed_bus_tye bus_type;
1433 + void __iomem *base;
1434 + u32 phy_base;
1435
1436 u32 wpdma_phys;
1437 u32 wpdma_int;
1438 u32 wpdma_mask;
1439 u32 wpdma_tx;
1440 u32 wpdma_txfree;
1441 + u32 wpdma_rx_glo;
1442 + u32 wpdma_rx;
1443 +
1444 + bool wcid_512;
1445
1446 u16 token_start;
1447 unsigned int nbuf;
1448 + unsigned int rx_nbuf;
1449 + unsigned int rx_npkt;
1450 + unsigned int rx_size;
1451
1452 u8 tx_tbit[MTK_WED_TX_QUEUES];
1453 + u8 rx_tbit[MTK_WED_RX_QUEUES];
1454 u8 txfree_tbit;
1455
1456 u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);
1457 int (*offload_enable)(struct mtk_wed_device *wed);
1458 void (*offload_disable)(struct mtk_wed_device *wed);
1459 + u32 (*init_rx_buf)(struct mtk_wed_device *wed, int size);
1460 + void (*release_rx_buf)(struct mtk_wed_device *wed);
1461 + void (*update_wo_rx_stats)(struct mtk_wed_device *wed,
1462 + struct mtk_wed_wo_rx_stats *stats);
1463 } wlan;
1464 #endif
1465 };
1466 @@ -107,9 +156,15 @@ struct mtk_wed_ops {
1467 int (*attach)(struct mtk_wed_device *dev);
1468 int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring,
1469 void __iomem *regs);
1470 + int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring,
1471 + void __iomem *regs);
1472 int (*txfree_ring_setup)(struct mtk_wed_device *dev,
1473 void __iomem *regs);
1474 + int (*msg_update)(struct mtk_wed_device *dev, int cmd_id,
1475 + void *data, int len);
1476 void (*detach)(struct mtk_wed_device *dev);
1477 + void (*ppe_check)(struct mtk_wed_device *dev, struct sk_buff *skb,
1478 + u32 reason, u32 hash);
1479
1480 void (*stop)(struct mtk_wed_device *dev);
1481 void (*start)(struct mtk_wed_device *dev, u32 irq_mask);
1482 @@ -144,6 +199,16 @@ mtk_wed_device_attach(struct mtk_wed_dev
1483 return ret;
1484 }
1485
1486 +static inline bool
1487 +mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
1488 +{
1489 +#ifdef CONFIG_NET_MEDIATEK_SOC_WED
1490 + return dev->version != 1;
1491 +#else
1492 + return false;
1493 +#endif
1494 +}
1495 +
1496 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
1497 #define mtk_wed_device_active(_dev) !!(_dev)->ops
1498 #define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)
1499 @@ -160,6 +225,12 @@ mtk_wed_device_attach(struct mtk_wed_dev
1500 (_dev)->ops->irq_get(_dev, _mask)
1501 #define mtk_wed_device_irq_set_mask(_dev, _mask) \
1502 (_dev)->ops->irq_set_mask(_dev, _mask)
1503 +#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) \
1504 + (_dev)->ops->rx_ring_setup(_dev, _ring, _regs)
1505 +#define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \
1506 + (_dev)->ops->ppe_check(_dev, _skb, _reason, _hash)
1507 +#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \
1508 + (_dev)->ops->msg_update(_dev, _id, _msg, _len)
1509 #else
1510 static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
1511 {
1512 @@ -173,6 +244,9 @@ static inline bool mtk_wed_device_active
1513 #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
1514 #define mtk_wed_device_irq_get(_dev, _mask) 0
1515 #define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)
1516 +#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) -ENODEV
1517 +#define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) do {} while (0)
1518 +#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) -ENODEV
1519 #endif
1520
1521 #endif
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