ef70de7ee4689cf8c7fbef0d437a6e00f42a9ebf
[openwrt/staging/pepe2k.git] /
1 From b1bd2f406eab321be642decd6aee6b6222aec62b Mon Sep 17 00:00:00 2001
2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
3 Date: Fri, 28 Jul 2023 17:40:27 +0100
4 Subject: [PATCH] drm/panel: simple: Alter the timing for the Pi 7" DSI display
5
6 vc4 has always fixed up the timing, so the values defined have
7 never actually appeared on the wire.
8 The display appears to want a slightly longer HFP, so extend
9 the timings and recompute the clock to give the same frame rate.
10
11 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
12 ---
13 drivers/gpu/drm/panel/panel-simple.c | 8 ++++----
14 1 file changed, 4 insertions(+), 4 deletions(-)
15
16 --- a/drivers/gpu/drm/panel/panel-simple.c
17 +++ b/drivers/gpu/drm/panel/panel-simple.c
18 @@ -3241,11 +3241,11 @@ static const struct panel_desc qishenglo
19 };
20
21 static const struct drm_display_mode raspberrypi_7inch_mode = {
22 - .clock = 25979400 / 1000,
23 + .clock = 27777,
24 .hdisplay = 800,
25 - .hsync_start = 800 + 2,
26 - .hsync_end = 800 + 2 + 2,
27 - .htotal = 800 + 2 + 2 + 46,
28 + .hsync_start = 800 + 59,
29 + .hsync_end = 800 + 59 + 2,
30 + .htotal = 800 + 59 + 2 + 46,
31 .vdisplay = 480,
32 .vsync_start = 480 + 7,
33 .vsync_end = 480 + 7 + 2,