git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 59c8adbc8e2c7f6b46385f36962eadaad3ea2daa Mon Sep 17 00:00:00 2001
   2 From: DENG Qingfang <dqfext@gmail.com>
   3 Date: Wed, 4 Aug 2021 00:04:01 +0800
   4 Subject: [PATCH] net: dsa: mt7530: enable assisted learning on CPU port
   5
   6 Consider the following bridge configuration, where bond0 is not
   7 offloaded:
   8
   9          +-- br0 --+
  10         / /   |     \
  11        / /    |      \
  12       /  |    |     bond0
  13      /   |    |     /   \
  14    swp0 swp1 swp2 swp3 swp4
  15      .        .       .
  16      .        .       .
  17      A        B       C
  18
  19 Address learning is enabled on offloaded ports (swp0~2) and the CPU
  20 port, so when client A sends a packet to C, the following will happen:
  21
  22 1. The switch learns that client A can be reached at swp0.
  23 2. The switch probably already knows that client C can be reached at the
  24    CPU port, so it forwards the packet to the CPU.
  25 3. The bridge core knows client C can be reached at bond0, so it
  26    forwards the packet back to the switch.
  27 4. The switch learns that client A can be reached at the CPU port.
  28 5. The switch forwards the packet to either swp3 or swp4, according to
  29    the packet's tag.
  30
  31 That makes client A's MAC address flap between swp0 and the CPU port. If
  32 client B sends a packet to A, it is possible that the packet is
  33 forwarded to the CPU. With offload_fwd_mark = 1, the bridge core won't
  34 forward it back to the switch, resulting in packet loss.
  35
  36 As we have the assisted_learning_on_cpu_port in DSA core now, enable
  37 that and disable hardware learning on the CPU port.
  38
  39 Signed-off-by: DENG Qingfang <dqfext@gmail.com>
  40 Reviewed-by: Vladimir Oltean <oltean@gmail.com>
  41 Signed-off-by: David S. Miller <davem@davemloft.net>
  42 ---
  43  drivers/net/dsa/mt7530.c | 14 ++++++++------
  44  1 file changed, 8 insertions(+), 6 deletions(-)
  45
  46 --- a/drivers/net/dsa/mt7530.c
  47 +++ b/drivers/net/dsa/mt7530.c
  48 @@ -1747,6 +1747,7 @@ mt7530_setup(struct dsa_switch *ds)
  49          */
  50         dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
  51         ds->configure_vlan_while_not_filtering = true;
  52 +       ds->assisted_learning_on_cpu_port = true;
  53         ds->mtu_enforcement_ingress = true;
  54
  55         if (priv->id == ID_MT7530) {
  56 @@ -1817,15 +1818,15 @@ mt7530_setup(struct dsa_switch *ds)
  57                 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
  58                            PCR_MATRIX_CLR);
  59
  60 +               /* Disable learning by default on all ports */
  61 +               mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
  62 +
  63                 if (dsa_is_cpu_port(ds, i)) {
  64                         ret = mt753x_cpu_port_enable(ds, i);
  65                         if (ret)
  66                                 return ret;
  67                 } else {
  68                         mt7530_port_disable(ds, i);
  69 -
  70 -                       /* Disable learning by default on all user ports */
  71 -                       mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
  72                 }
  73
  74                 /* Enable consistent egress tag */
  75 @@ -1981,6 +1982,9 @@ mt7531_setup(struct dsa_switch *ds)
  76                 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
  77                            PCR_MATRIX_CLR);
  78
  79 +               /* Disable learning by default on all ports */
  80 +               mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
  81 +
  82                 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
  83
  84                 if (dsa_is_cpu_port(ds, i)) {
  85 @@ -1989,9 +1993,6 @@ mt7531_setup(struct dsa_switch *ds)
  86                                 return ret;
  87                 } else {
  88                         mt7530_port_disable(ds, i);
  89 -
  90 -                       /* Disable learning by default on all user ports */
  91 -                       mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
  92                 }
  93
  94                 /* Enable consistent egress tag */
  95 @@ -2000,6 +2001,7 @@ mt7531_setup(struct dsa_switch *ds)
  96         }
  97
  98         ds->configure_vlan_while_not_filtering = true;
  99 +       ds->assisted_learning_on_cpu_port = true;
 100         ds->mtu_enforcement_ingress = true;
 101
 102         /* Flush the FDB table */