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1 From ba4acf55044a8a11fc7e11a558a8a93e3c126391 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 29 Jul 2022 11:21:59 +0800
4 Subject: [PATCH 26/31] clk: mediatek: add clock driver support for MediaTek
5 MT7986 SoC
6
7 This patch adds clock driver support for MediaTek MT7986 SoC
8
9 Reviewed-by: Simon Glass <sjg@chromium.org>
10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
11 ---
12 drivers/clk/mediatek/Makefile | 1 +
13 drivers/clk/mediatek/clk-mt7986.c | 672 +++++++++++++++++++++++++
14 include/dt-bindings/clock/mt7986-clk.h | 249 +++++++++
15 3 files changed, 922 insertions(+)
16 create mode 100644 drivers/clk/mediatek/clk-mt7986.c
17 create mode 100644 include/dt-bindings/clock/mt7986-clk.h
18
19 --- a/drivers/clk/mediatek/Makefile
20 +++ b/drivers/clk/mediatek/Makefile
21 @@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o
22 obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
23 obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
24 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
25 +obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
26 obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
27 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
28 obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
29 --- /dev/null
30 +++ b/drivers/clk/mediatek/clk-mt7986.c
31 @@ -0,0 +1,672 @@
32 +// SPDX-License-Identifier: GPL-2.0
33 +/*
34 + * MediaTek clock driver for MT7986 SoC
35 + *
36 + * Copyright (C) 2022 MediaTek Inc.
37 + * Author: Sam Shih <sam.shih@mediatek.com>
38 + */
39 +
40 +#include <dm.h>
41 +#include <log.h>
42 +#include <asm/arch-mediatek/reset.h>
43 +#include <asm/io.h>
44 +#include <dt-bindings/clock/mt7986-clk.h>
45 +#include <linux/bitops.h>
46 +
47 +#include "clk-mtk.h"
48 +
49 +#define MT7986_CLK_PDN 0x250
50 +#define MT7986_CLK_PDN_EN_WRITE BIT(31)
51 +
52 +#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
53 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
54 +
55 +#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \
56 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
57 +
58 +#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \
59 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
60 +
61 +/* FIXED PLLS */
62 +static const struct mtk_fixed_clk fixed_pll_clks[] = {
63 + FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
64 + FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
65 + FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
66 + FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
67 + FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
68 + FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
69 + FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
70 + FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
71 +};
72 +
73 +/* TOPCKGEN FIXED CLK */
74 +static const struct mtk_fixed_clk top_fixed_clks[] = {
75 + FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
76 +};
77 +
78 +/* TOPCKGEN FIXED DIV */
79 +static const struct mtk_fixed_factor top_fixed_divs[] = {
80 + PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
81 + PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
82 + PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
83 + PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
84 + PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
85 + PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
86 + PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
87 + PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
88 + PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
89 + PLL_FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", CK_APMIXED_MMPLL, 1, 16),
90 + PLL_FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", CK_APMIXED_MMPLL, 1, 8),
91 + PLL_FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", CK_APMIXED_MMPLL, 1, 30),
92 + PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
93 + 1),
94 + PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
95 + PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
96 + PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
97 + PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
98 + PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
99 + PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
100 + PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
101 + PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
102 + 1),
103 + PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
104 + PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
105 + PLL_FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
106 + PLL_FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m",
107 + CK_APMIXED_WEDMCUPLL, 1, 1),
108 + PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
109 + 10),
110 + PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
111 + TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M,
112 + 1, 2),
113 + TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
114 + 1250),
115 + TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
116 + 1220),
117 + TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
118 + TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
119 + 1),
120 + TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
121 + TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
122 + TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
123 + TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
124 + TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
125 + TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
126 + TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
127 + TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
128 + TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
129 + 1),
130 + TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
131 + TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
132 + CK_TOP_NETSYS_MCU_SEL, 1, 1),
133 + TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
134 + TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
135 + TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
136 + TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
137 + TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
138 + TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
139 + TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
140 + TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
141 + TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
142 + TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
143 + TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
144 + 1),
145 +};
146 +
147 +/* TOPCKGEN MUX PARENTS */
148 +static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D8,
149 + CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2,
150 + CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2,
151 + CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 };
152 +
153 +static const int spinfi_parents[] = {
154 + CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
155 + CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2,
156 + CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8
157 +};
158 +
159 +static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
160 + CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2,
161 + CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4,
162 + CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 };
163 +
164 +static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
165 + CK_TOP_M_D8_D2 };
166 +
167 +static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
168 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
169 +
170 +static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
171 + CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
172 +
173 +static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
174 + CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2,
175 + CK_TOP_CB_RTC_32K };
176 +
177 +static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
178 + CK_TOP_NET1_D5_D2 };
179 +
180 +static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M };
181 +
182 +static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
183 +
184 +static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 };
185 +
186 +static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
187 + CK_TOP_CB_NET2_D4 };
188 +
189 +static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2,
190 + CK_TOP_NET2_D4_D2 };
191 +
192 +static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
193 + CK_TOP_NET2_D3_D2 };
194 +
195 +static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M };
196 +
197 +static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 };
198 +
199 +static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
200 + CK_TOP_CB_NET1_D5 };
201 +
202 +static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M,
203 + CK_TOP_CB_WEDMCU_760M,
204 + CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4,
205 + CK_TOP_CB_NET1_D5 };
206 +
207 +static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
208 + CK_TOP_CB_NET2_800M,
209 + CK_TOP_CB_WEDMCU_760M,
210 + CK_TOP_CB_MM_D2 };
211 +
212 +static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
213 + CK_TOP_CB_SGM_325M };
214 +
215 +static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 };
216 +
217 +static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
218 +
219 +static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M,
220 + CK_TOP_CB_MM_D2 };
221 +
222 +static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M };
223 +
224 +static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
225 + CK_TOP_M_D8_D2 };
226 +
227 +static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
228 + CK_TOP_M_D8_D2 };
229 +
230 +static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
231 +
232 +static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M,
233 + CK_TOP_CB_U2_PHYD_CK };
234 +
235 +#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
236 + _shift, _width, _gate, _upd_ofs, _upd) \
237 + { \
238 + .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \
239 + .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
240 + .upd_shift = _upd, .mux_shift = _shift, \
241 + .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
242 + .gate_shift = _gate, .parent = _parents, \
243 + .num_parents = ARRAY_SIZE(_parents), \
244 + .flags = CLK_MUX_SETCLR_UPD, \
245 + }
246 +
247 +/* TOPCKGEN MUX_GATE */
248 +static const struct mtk_composite top_muxes[] = {
249 + /* CLK_CFG_0 */
250 + TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
251 + 0x008, 0, 3, 7, 0x1C0, 0),
252 + TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
253 + 0x008, 8, 3, 15, 0x1C0, 1),
254 + TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
255 + 3, 23, 0x1C0, 2),
256 + TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
257 + 0x008, 24, 3, 31, 0x1C0, 3),
258 + /* CLK_CFG_1 */
259 + TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
260 + 0, 2, 7, 0x1C0, 4),
261 + TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
262 + 2, 15, 0x1C0, 5),
263 + TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
264 + 2, 23, 0x1C0, 6),
265 + TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
266 + 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7),
267 + /* CLK_CFG_2 */
268 + TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
269 + 0x024, 0x028, 0, 1, 7, 0x1C0, 8),
270 + TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
271 + 0x024, 0x028, 8, 1, 15, 0x1C0, 9),
272 + TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
273 + 0x024, 0x028, 16, 1, 23, 0x1C0, 10),
274 + TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
275 + 0x028, 24, 1, 31, 0x1C0, 11),
276 + /* CLK_CFG_3 */
277 + TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
278 + 0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12),
279 + TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
280 + 0x038, 8, 2, 15, 0x1C0, 13),
281 + TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
282 + 0x038, 16, 2, 23, 0x1C0, 14),
283 + TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
284 + 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15),
285 + /* CLK_CFG_4 */
286 + TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
287 + 0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16),
288 + TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
289 + 0x048, 8, 1, 15, 0x1C0, 17),
290 + TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
291 + 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
292 + TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
293 + 0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
294 + /* CLK_CFG_5 */
295 + TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
296 + 0x054, 0x058, 0, 2, 7, 0x1C0, 20),
297 + TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
298 + 0x054, 0x058, 8, 1, 15, 0x1C0, 21),
299 + TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
300 + 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
301 + TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
302 + 0x058, 24, 1, 31, 0x1C0, 23),
303 + /* CLK_CFG_6 */
304 + TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
305 + 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
306 + TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
307 + 0x068, 8, 1, 15, 0x1C0, 25),
308 + TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
309 + 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
310 + TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
311 + 0x064, 0x068, 24, 1, 31, 0x1C0, 27),
312 + /* CLK_CFG_7 */
313 + TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
314 + 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
315 + TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
316 + 0x078, 8, 2, 15, 0x1C0, 29),
317 + TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
318 + 0x074, 0x078, 16, 2, 23, 0x1C0, 30),
319 + TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
320 + 0x078, 24, 1, 31, 0x1C4, 0),
321 + /* CLK_CFG_8 */
322 + TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
323 + 0x084, 0x088, 0, 1, 7, 0x1C4, 1),
324 + TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
325 + 0x084, 0x088, 8, 1, 15, 0x1C4, 2),
326 + TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
327 + 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
328 + TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
329 + 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
330 + /* CLK_CFG_9 */
331 + TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
332 + 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
333 +};
334 +
335 +/* INFRA FIXED DIV */
336 +static const struct mtk_fixed_factor infra_fixed_divs[] = {
337 + TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
338 + TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
339 + TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
340 + TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
341 + TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1),
342 + TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
343 + TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
344 + TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
345 + 1),
346 + TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
347 + INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
348 + 1),
349 + INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
350 + 1),
351 + INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
352 + 1),
353 + TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
354 + TOP_FACTOR(CK_INFRA_EIP_CK, "infra_eip", CK_TOP_EIP_B, 1, 1),
355 + INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
356 + 1),
357 + TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
358 + TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
359 + TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
360 + 1),
361 + TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
362 + INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
363 + 1, 1),
364 + INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
365 + 1, 1),
366 + INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
367 + 1, 1),
368 + TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
369 + TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
370 + INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
371 + 1),
372 + INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
373 + 1),
374 + TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
375 + TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_416M, 1, 1),
376 + TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_250M,
377 + 1, 1),
378 + TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
379 + TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
380 + TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
381 + TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
382 + TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
383 + 1),
384 + TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
385 + CK_TOP_PEXTP_TL, 1, 1),
386 + TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
387 + TOP_FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", CK_TOP_SYSAXI, 1, 1),
388 +};
389 +
390 +/* INFRASYS MUX PARENTS */
391 +static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
392 +
393 +static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
394 +
395 +static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
396 +
397 +static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K,
398 + CK_INFRA_CK_F26M,
399 + CK_INFRA_66M_MCK, CK_INFRA_PWM };
400 +
401 +static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
402 + -1, CK_INFRA_PCIE_CK };
403 +
404 +#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
405 + { \
406 + .id = _id, .mux_reg = (_reg) + 0x8, \
407 + .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
408 + .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
409 + .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
410 + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
411 + }
412 +
413 +/* INFRA MUX */
414 +
415 +static const struct mtk_composite infra_muxes[] = {
416 + /* MODULE_CLK_SEL_0 */
417 + INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
418 + 0x10, 0, 1),
419 + INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
420 + 0x10, 1, 1),
421 + INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
422 + 0x10, 2, 1),
423 + INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
424 + 4, 1),
425 + INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
426 + 5, 1),
427 + INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
428 + 0x10, 9, 2),
429 + INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
430 + 0x10, 11, 2),
431 + INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
432 + 0x10, 13, 2),
433 + /* MODULE_CLK_SEL_1 */
434 + INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
435 + 0, 2),
436 +};
437 +
438 +static const struct mtk_gate_regs infra_0_cg_regs = {
439 + .set_ofs = 0x40,
440 + .clr_ofs = 0x44,
441 + .sta_ofs = 0x48,
442 +};
443 +
444 +static const struct mtk_gate_regs infra_1_cg_regs = {
445 + .set_ofs = 0x50,
446 + .clr_ofs = 0x54,
447 + .sta_ofs = 0x58,
448 +};
449 +
450 +static const struct mtk_gate_regs infra_2_cg_regs = {
451 + .set_ofs = 0x60,
452 + .clr_ofs = 0x64,
453 + .sta_ofs = 0x68,
454 +};
455 +
456 +#define GATE_INFRA0(_id, _name, _parent, _shift) \
457 + { \
458 + .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
459 + .shift = _shift, \
460 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
461 + }
462 +
463 +#define GATE_INFRA1(_id, _name, _parent, _shift) \
464 + { \
465 + .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
466 + .shift = _shift, \
467 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
468 + }
469 +
470 +#define GATE_INFRA2(_id, _name, _parent, _shift) \
471 + { \
472 + .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
473 + .shift = _shift, \
474 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
475 + }
476 +
477 +/* INFRA GATE */
478 +
479 +static const struct mtk_gate infracfg_ao_gates[] = {
480 + /* INFRA0 */
481 + GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
482 + GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
483 + GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
484 + GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
485 + GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
486 + GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
487 + GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", CK_INFRA_EIP_CK, 7),
488 + GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
489 + GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
490 + GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
491 + GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
492 + 11),
493 + GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
494 + 13),
495 + GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
496 + 14),
497 + GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
498 + GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
499 + GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
500 + GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
501 + GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26),
502 + /* INFRA1 */
503 + GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
504 + GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
505 + GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
506 + GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
507 + GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
508 + GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
509 + GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
510 + 9),
511 + GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
512 + GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
513 + GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
514 + GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
515 + 13),
516 + GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
517 + 14),
518 + GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
519 + GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
520 + GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
521 + CK_INFRA_FMSDC_HCK_CK, 17),
522 + GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
523 + CK_INFRA_PERI_133M, 18),
524 + GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
525 + 19),
526 + GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_CK_F26M, 20),
527 + GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21),
528 + GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
529 + 23),
530 + /* INFRA2 */
531 + GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
532 + 0),
533 + GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
534 + 1),
535 + GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
536 + 2),
537 + GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
538 + GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13),
539 + GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15),
540 + GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
541 +};
542 +
543 +static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
544 + .fdivs_offs = CLK_APMIXED_NR_CLK,
545 + .xtal_rate = 40 * MHZ,
546 + .fclks = fixed_pll_clks,
547 +};
548 +
549 +static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
550 + .fdivs_offs = CK_TOP_CB_M_416M,
551 + .muxes_offs = CK_TOP_NFI1X_SEL,
552 + .fclks = top_fixed_clks,
553 + .fdivs = top_fixed_divs,
554 + .muxes = top_muxes,
555 + .flags = CLK_BYPASS_XTAL,
556 +};
557 +
558 +static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
559 + .fdivs_offs = CK_INFRA_CK_F26M,
560 + .muxes_offs = CK_INFRA_UART0_SEL,
561 + .fdivs = infra_fixed_divs,
562 + .muxes = infra_muxes,
563 +};
564 +
565 +static const struct udevice_id mt7986_fixed_pll_compat[] = {
566 + { .compatible = "mediatek,mt7986-fixed-plls" },
567 + {}
568 +};
569 +
570 +static const struct udevice_id mt7986_topckgen_compat[] = {
571 + { .compatible = "mediatek,mt7986-topckgen" },
572 + {}
573 +};
574 +
575 +static int mt7986_fixed_pll_probe(struct udevice *dev)
576 +{
577 + return mtk_common_clk_init(dev, &mt7986_fixed_pll_clk_tree);
578 +}
579 +
580 +static int mt7986_topckgen_probe(struct udevice *dev)
581 +{
582 + struct mtk_clk_priv *priv = dev_get_priv(dev);
583 +
584 + priv->base = dev_read_addr_ptr(dev);
585 + writel(MT7986_CLK_PDN_EN_WRITE, priv->base + MT7986_CLK_PDN);
586 +
587 + return mtk_common_clk_init(dev, &mt7986_topckgen_clk_tree);
588 +}
589 +
590 +U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
591 + .name = "mt7986-clock-fixed-pll",
592 + .id = UCLASS_CLK,
593 + .of_match = mt7986_fixed_pll_compat,
594 + .probe = mt7986_fixed_pll_probe,
595 + .priv_auto = sizeof(struct mtk_clk_priv),
596 + .ops = &mtk_clk_topckgen_ops,
597 + .flags = DM_FLAG_PRE_RELOC,
598 +};
599 +
600 +U_BOOT_DRIVER(mtk_clk_topckgen) = {
601 + .name = "mt7986-clock-topckgen",
602 + .id = UCLASS_CLK,
603 + .of_match = mt7986_topckgen_compat,
604 + .probe = mt7986_topckgen_probe,
605 + .priv_auto = sizeof(struct mtk_clk_priv),
606 + .ops = &mtk_clk_topckgen_ops,
607 + .flags = DM_FLAG_PRE_RELOC,
608 +};
609 +
610 +static const struct udevice_id mt7986_infracfg_compat[] = {
611 + { .compatible = "mediatek,mt7986-infracfg" },
612 + {}
613 +};
614 +
615 +static const struct udevice_id mt7986_infracfg_ao_compat[] = {
616 + { .compatible = "mediatek,mt7986-infracfg_ao" },
617 + {}
618 +};
619 +
620 +static int mt7986_infracfg_probe(struct udevice *dev)
621 +{
622 + return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
623 +}
624 +
625 +static int mt7986_infracfg_ao_probe(struct udevice *dev)
626 +{
627 + return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree,
628 + infracfg_ao_gates);
629 +}
630 +
631 +U_BOOT_DRIVER(mtk_clk_infracfg) = {
632 + .name = "mt7986-clock-infracfg",
633 + .id = UCLASS_CLK,
634 + .of_match = mt7986_infracfg_compat,
635 + .probe = mt7986_infracfg_probe,
636 + .priv_auto = sizeof(struct mtk_clk_priv),
637 + .ops = &mtk_clk_infrasys_ops,
638 + .flags = DM_FLAG_PRE_RELOC,
639 +};
640 +
641 +U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
642 + .name = "mt7986-clock-infracfg-ao",
643 + .id = UCLASS_CLK,
644 + .of_match = mt7986_infracfg_ao_compat,
645 + .probe = mt7986_infracfg_ao_probe,
646 + .priv_auto = sizeof(struct mtk_cg_priv),
647 + .ops = &mtk_clk_gate_ops,
648 + .flags = DM_FLAG_PRE_RELOC,
649 +};
650 +
651 +/* ethsys */
652 +static const struct mtk_gate_regs eth_cg_regs = {
653 + .sta_ofs = 0x30,
654 +};
655 +
656 +#define GATE_ETH(_id, _name, _parent, _shift) \
657 + { \
658 + .id = _id, .parent = _parent, .regs = &eth_cg_regs, \
659 + .shift = _shift, \
660 + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
661 + }
662 +
663 +static const struct mtk_gate eth_cgs[] = {
664 + GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7),
665 + GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8),
666 + GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
667 + GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 14),
668 + GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
669 +};
670 +
671 +static int mt7986_ethsys_probe(struct udevice *dev)
672 +{
673 + return mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree,
674 + eth_cgs);
675 +}
676 +
677 +static int mt7986_ethsys_bind(struct udevice *dev)
678 +{
679 + int ret = 0;
680 +
681 + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
682 + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
683 + if (ret)
684 + debug("Warning: failed to bind reset controller\n");
685 + }
686 +
687 + return ret;
688 +}
689 +
690 +static const struct udevice_id mt7986_ethsys_compat[] = {
691 + { .compatible = "mediatek,mt7986-ethsys" },
692 + { }
693 +};
694 +
695 +U_BOOT_DRIVER(mtk_clk_ethsys) = {
696 + .name = "mt7986-clock-ethsys",
697 + .id = UCLASS_CLK,
698 + .of_match = mt7986_ethsys_compat,
699 + .probe = mt7986_ethsys_probe,
700 + .bind = mt7986_ethsys_bind,
701 + .priv_auto = sizeof(struct mtk_cg_priv),
702 + .ops = &mtk_clk_gate_ops,
703 +};
704 --- /dev/null
705 +++ b/include/dt-bindings/clock/mt7986-clk.h
706 @@ -0,0 +1,249 @@
707 +/* SPDX-License-Identifier: GPL-2.0 */
708 +/*
709 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
710 + *
711 + * Author: Sam Shih <sam.shih@mediatek.com>
712 + */
713 +
714 +#ifndef _DT_BINDINGS_CLK_MT7986_H
715 +#define _DT_BINDINGS_CLK_MT7986_H
716 +
717 +/* INFRACFG */
718 +
719 +#define CK_INFRA_CK_F26M 0
720 +#define CK_INFRA_UART 1
721 +#define CK_INFRA_ISPI0 2
722 +#define CK_INFRA_I2C 3
723 +#define CK_INFRA_ISPI1 4
724 +#define CK_INFRA_PWM 5
725 +#define CK_INFRA_66M_MCK 6
726 +#define CK_INFRA_CK_F32K 7
727 +#define CK_INFRA_PCIE_CK 8
728 +#define CK_INFRA_PWM_BCK 9
729 +#define CK_INFRA_PWM_CK1 10
730 +#define CK_INFRA_PWM_CK2 11
731 +#define CK_INFRA_133M_HCK 12
732 +#define CK_INFRA_EIP_CK 13
733 +#define CK_INFRA_66M_PHCK 14
734 +#define CK_INFRA_FAUD_L_CK 15
735 +#define CK_INFRA_FAUD_AUD_CK 17
736 +#define CK_INFRA_FAUD_EG2_CK 17
737 +#define CK_INFRA_I2CS_CK 18
738 +#define CK_INFRA_MUX_UART0 19
739 +#define CK_INFRA_MUX_UART1 20
740 +#define CK_INFRA_MUX_UART2 21
741 +#define CK_INFRA_NFI_CK 22
742 +#define CK_INFRA_SPINFI_CK 23
743 +#define CK_INFRA_MUX_SPI0 24
744 +#define CK_INFRA_MUX_SPI1 25
745 +#define CK_INFRA_RTC_32K 26
746 +#define CK_INFRA_FMSDC_CK 27
747 +#define CK_INFRA_FMSDC_HCK_CK 28
748 +#define CK_INFRA_PERI_133M 29
749 +#define CK_INFRA_133M_PHCK 30
750 +#define CK_INFRA_USB_SYS_CK 31
751 +#define CK_INFRA_USB_CK 32
752 +#define CK_INFRA_USB_XHCI_CK 33
753 +#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
754 +#define CK_INFRA_F26M_CK0 35
755 +#define CK_INFRA_HD_133M 36
756 +#define CLK_INFRA_NR_CLK 37
757 +
758 +/* TOPCKGEN */
759 +
760 +#define CK_TOP_CB_CKSQ_40M 0
761 +#define CK_TOP_CB_M_416M 1
762 +#define CK_TOP_CB_M_D2 2
763 +#define CK_TOP_CB_M_D4 3
764 +#define CK_TOP_CB_M_D8 4
765 +#define CK_TOP_M_D8_D2 5
766 +#define CK_TOP_M_D3_D2 6
767 +#define CK_TOP_CB_MM_D2 7
768 +#define CK_TOP_CB_MM_D4 8
769 +#define CK_TOP_CB_MM_D8 9
770 +#define CK_TOP_MM_D8_D2 10
771 +#define CK_TOP_MM_D3_D8 11
772 +#define CK_TOP_CB_U2_PHYD_CK 12
773 +#define CK_TOP_CB_APLL2_196M 13
774 +#define CK_TOP_APLL2_D4 14
775 +#define CK_TOP_CB_NET1_D4 15
776 +#define CK_TOP_CB_NET1_D5 16
777 +#define CK_TOP_NET1_D5_D2 17
778 +#define CK_TOP_NET1_D5_D4 18
779 +#define CK_TOP_NET1_D8_D2 19
780 +#define CK_TOP_NET1_D8_D4 20
781 +#define CK_TOP_CB_NET2_800M 21
782 +#define CK_TOP_CB_NET2_D4 22
783 +#define CK_TOP_NET2_D4_D2 23
784 +#define CK_TOP_NET2_D3_D2 24
785 +#define CK_TOP_CB_WEDMCU_760M 25
786 +#define CK_TOP_WEDMCU_D5_D2 26
787 +#define CK_TOP_CB_SGM_325M 27
788 +#define CK_TOP_CB_CKSQ_40M_D2 28
789 +#define CK_TOP_CB_RTC_32K 29
790 +#define CK_TOP_CB_RTC_32P7K 30
791 +#define CK_TOP_NFI1X 31
792 +#define CK_TOP_USB_EQ_RX250M 32
793 +#define CK_TOP_USB_TX250M 33
794 +#define CK_TOP_USB_LN0_CK 34
795 +#define CK_TOP_USB_CDR_CK 35
796 +#define CK_TOP_SPINFI_BCK 36
797 +#define CK_TOP_I2C_BCK 37
798 +#define CK_TOP_PEXTP_TL 38
799 +#define CK_TOP_EMMC_250M 39
800 +#define CK_TOP_EMMC_416M 40
801 +#define CK_TOP_F_26M_ADC_CK 41
802 +#define CK_TOP_SYSAXI 42
803 +#define CK_TOP_NETSYS_WED_MCU 43
804 +#define CK_TOP_NETSYS_2X 44
805 +#define CK_TOP_SGM_325M 45
806 +#define CK_TOP_A1SYS 46
807 +#define CK_TOP_EIP_B 47
808 +#define CK_TOP_F26M 48
809 +#define CK_TOP_AUD_L 49
810 +#define CK_TOP_A_TUNER 50
811 +#define CK_TOP_U2U3_REF 51
812 +#define CK_TOP_U2U3_SYS 52
813 +#define CK_TOP_U2U3_XHCI 53
814 +#define CK_TOP_AP2CNN_HOST 54
815 +#define CK_TOP_NFI1X_SEL 55
816 +#define CK_TOP_SPINFI_SEL 56
817 +#define CK_TOP_SPI_SEL 57
818 +#define CK_TOP_SPIM_MST_SEL 58
819 +#define CK_TOP_UART_SEL 59
820 +#define CK_TOP_PWM_SEL 60
821 +#define CK_TOP_I2C_SEL 61
822 +#define CK_TOP_PEXTP_TL_SEL 62
823 +#define CK_TOP_EMMC_250M_SEL 63
824 +#define CK_TOP_EMMC_416M_SEL 64
825 +#define CK_TOP_F_26M_ADC_SEL 65
826 +#define CK_TOP_DRAMC_SEL 66
827 +#define CK_TOP_DRAMC_MD32_SEL 67
828 +#define CK_TOP_SYSAXI_SEL 68
829 +#define CK_TOP_SYSAPB_SEL 69
830 +#define CK_TOP_ARM_DB_MAIN_SEL 70
831 +#define CK_TOP_ARM_DB_JTSEL 71
832 +#define CK_TOP_NETSYS_SEL 72
833 +#define CK_TOP_NETSYS_500M_SEL 73
834 +#define CK_TOP_NETSYS_MCU_SEL 74
835 +#define CK_TOP_NETSYS_2X_SEL 75
836 +#define CK_TOP_SGM_325M_SEL 76
837 +#define CK_TOP_SGM_REG_SEL 77
838 +#define CK_TOP_A1SYS_SEL 78
839 +#define CK_TOP_CONN_MCUSYS_SEL 79
840 +#define CK_TOP_EIP_B_SEL 80
841 +#define CK_TOP_PCIE_PHY_SEL 81
842 +#define CK_TOP_USB3_PHY_SEL 82
843 +#define CK_TOP_F26M_SEL 83
844 +#define CK_TOP_AUD_L_SEL 84
845 +#define CK_TOP_A_TUNER_SEL 85
846 +#define CK_TOP_U2U3_SEL 86
847 +#define CK_TOP_U2U3_SYS_SEL 87
848 +#define CK_TOP_U2U3_XHCI_SEL 88
849 +#define CK_TOP_DA_U2_REFSEL 89
850 +#define CK_TOP_DA_U2_CK_1P_SEL 90
851 +#define CK_TOP_AP2CNN_HOST_SEL 91
852 +#define CLK_TOP_NR_CLK 92
853 +
854 +/*
855 + * INFRACFG_AO
856 + * clock muxes need to be append to infracfg domain, and clock gates
857 + * need to be keep in infracgh_ao domain
858 + */
859 +
860 +#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
861 +#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
862 +#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
863 +#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
864 +#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
865 +#define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
866 +#define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
867 +#define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
868 +#define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
869 +#define CK_INFRA_GPT_STA 0
870 +#define CK_INFRA_PWM_HCK 1
871 +#define CK_INFRA_PWM_STA 2
872 +#define CK_INFRA_PWM1_CK 3
873 +#define CK_INFRA_PWM2_CK 4
874 +#define CK_INFRA_CQ_DMA_CK 5
875 +#define CK_INFRA_EIP97_CK 6
876 +#define CK_INFRA_AUD_BUS_CK 7
877 +#define CK_INFRA_AUD_26M_CK 8
878 +#define CK_INFRA_AUD_L_CK 9
879 +#define CK_INFRA_AUD_AUD_CK 10
880 +#define CK_INFRA_AUD_EG2_CK 11
881 +#define CK_INFRA_DRAMC_26M_CK 12
882 +#define CK_INFRA_DBG_CK 13
883 +#define CK_INFRA_AP_DMA_CK 14
884 +#define CK_INFRA_SEJ_CK 15
885 +#define CK_INFRA_SEJ_13M_CK 16
886 +#define CK_INFRA_THERM_CK 17
887 +#define CK_INFRA_I2CO_CK 18
888 +#define CK_INFRA_TRNG_CK 19
889 +#define CK_INFRA_UART0_CK 20
890 +#define CK_INFRA_UART1_CK 21
891 +#define CK_INFRA_UART2_CK 22
892 +#define CK_INFRA_NFI1_CK 23
893 +#define CK_INFRA_SPINFI1_CK 24
894 +#define CK_INFRA_NFI_HCK_CK 25
895 +#define CK_INFRA_SPI0_CK 26
896 +#define CK_INFRA_SPI1_CK 27
897 +#define CK_INFRA_SPI0_HCK_CK 28
898 +#define CK_INFRA_SPI1_HCK_CK 29
899 +#define CK_INFRA_FRTC_CK 30
900 +#define CK_INFRA_MSDC_CK 31
901 +#define CK_INFRA_MSDC_HCK_CK 32
902 +#define CK_INFRA_MSDC_133M_CK 33
903 +#define CK_INFRA_MSDC_66M_CK 34
904 +#define CK_INFRA_ADC_26M_CK 35
905 +#define CK_INFRA_ADC_FRC_CK 36
906 +#define CK_INFRA_FBIST2FPC_CK 37
907 +#define CK_INFRA_IUSB_133_CK 38
908 +#define CK_INFRA_IUSB_66M_CK 39
909 +#define CK_INFRA_IUSB_SYS_CK 40
910 +#define CK_INFRA_IUSB_CK 41
911 +#define CK_INFRA_IPCIE_CK 42
912 +#define CK_INFRA_IPCIER_CK 43
913 +#define CK_INFRA_IPCIEB_CK 44
914 +#define CLK_INFRA_AO_NR_CLK 45
915 +
916 +/* APMIXEDSYS */
917 +
918 +#define CK_APMIXED_ARMPLL 0
919 +#define CK_APMIXED_NET2PLL 1
920 +#define CK_APMIXED_MMPLL 2
921 +#define CK_APMIXED_SGMPLL 3
922 +#define CK_APMIXED_WEDMCUPLL 4
923 +#define CK_APMIXED_NET1PLL 5
924 +#define CK_APMIXED_MPLL 6
925 +#define CK_APMIXED_APLL2 7
926 +#define CLK_APMIXED_NR_CLK 8
927 +
928 +/* SGMIISYS_0 */
929 +
930 +#define CK_SGM0_TX_EN 0
931 +#define CK_SGM0_RX_EN 1
932 +#define CK_SGM0_CK0_EN 2
933 +#define CK_SGM0_CDR_CK0_EN 3
934 +#define CLK_SGMII0_NR_CLK 4
935 +
936 +/* SGMIISYS_1 */
937 +
938 +#define CK_SGM1_TX_EN 0
939 +#define CK_SGM1_RX_EN 1
940 +#define CK_SGM1_CK1_EN 2
941 +#define CK_SGM1_CDR_CK1_EN 3
942 +#define CLK_SGMII1_NR_CLK 4
943 +
944 +/* ETHSYS */
945 +
946 +#define CK_ETH_FE_EN 0
947 +#define CK_ETH_GP2_EN 1
948 +#define CK_ETH_GP1_EN 2
949 +#define CK_ETH_WOCPU1_EN 3
950 +#define CK_ETH_WOCPU0_EN 4
951 +#define CLK_ETH_NR_CLK 5
952 +
953 +#endif
954 +
955 +/* _DT_BINDINGS_CLK_MT7986_H */
Staging tree of Matthias Schiffer