git.openwrt.org Git - openwrt/staging/svanheule.git/blob

   1 From b8bdfc666bc5f58caf46e67b615132fccbaca3d4 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Tue, 12 Nov 2024 01:08:50 +0100
   4 Subject: [PATCH 2/6] clk: en7523: move clock_register in hw_init callback
   5
   6 Move en7523_register_clocks routine in hw_init callback.
   7 Introduce en7523_clk_hw_init callback for EN7523 SoC.
   8 This is a preliminary patch to differentiate IO mapped region between
   9 EN7523 and EN7581 SoCs in order to access chip-scu IO region
  10 <0x1fa20000 0x384> on EN7581 SoC as syscon device since it contains
  11 miscellaneous registers needed by multiple devices (clock, pinctrl ..).
  12
  13 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  14 Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-3-8ada5e394ae4@kernel.org
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  drivers/clk/clk-en7523.c | 82 ++++++++++++++++++++++++----------------
  18  1 file changed, 50 insertions(+), 32 deletions(-)
  19
  20 --- a/drivers/clk/clk-en7523.c
  21 +++ b/drivers/clk/clk-en7523.c
  22 @@ -78,7 +78,8 @@ struct en_clk_soc_data {
  23                 const u16 *idx_map;
  24                 u16 idx_map_nr;
  25         } reset;
  26 -       int (*hw_init)(struct platform_device *pdev, void __iomem *np_base);
  27 +       int (*hw_init)(struct platform_device *pdev,
  28 +                      struct clk_hw_onecell_data *clk_data);
  29  };
  30
  31  static const u32 gsw_base[] = { 400000000, 500000000 };
  32 @@ -406,20 +407,6 @@ static void en7581_pci_disable(struct cl
  33         usleep_range(1000, 2000);
  34  }
  35
  36 -static int en7581_clk_hw_init(struct platform_device *pdev,
  37 -                             void __iomem *np_base)
  38 -{
  39 -       u32 val;
  40 -
  41 -       val = readl(np_base + REG_NP_SCU_SSTR);
  42 -       val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
  43 -       writel(val, np_base + REG_NP_SCU_SSTR);
  44 -       val = readl(np_base + REG_NP_SCU_PCIC);
  45 -       writel(val | 3, np_base + REG_NP_SCU_PCIC);
  46 -
  47 -       return 0;
  48 -}
  49 -
  50  static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
  51                                    void __iomem *base, void __iomem *np_base)
  52  {
  53 @@ -449,6 +436,49 @@ static void en7523_register_clocks(struc
  54         clk_data->num = EN7523_NUM_CLOCKS;
  55  }
  56
  57 +static int en7523_clk_hw_init(struct platform_device *pdev,
  58 +                             struct clk_hw_onecell_data *clk_data)
  59 +{
  60 +       void __iomem *base, *np_base;
  61 +
  62 +       base = devm_platform_ioremap_resource(pdev, 0);
  63 +       if (IS_ERR(base))
  64 +               return PTR_ERR(base);
  65 +
  66 +       np_base = devm_platform_ioremap_resource(pdev, 1);
  67 +       if (IS_ERR(np_base))
  68 +               return PTR_ERR(np_base);
  69 +
  70 +       en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
  71 +
  72 +       return 0;
  73 +}
  74 +
  75 +static int en7581_clk_hw_init(struct platform_device *pdev,
  76 +                             struct clk_hw_onecell_data *clk_data)
  77 +{
  78 +       void __iomem *base, *np_base;
  79 +       u32 val;
  80 +
  81 +       base = devm_platform_ioremap_resource(pdev, 0);
  82 +       if (IS_ERR(base))
  83 +               return PTR_ERR(base);
  84 +
  85 +       np_base = devm_platform_ioremap_resource(pdev, 1);
  86 +       if (IS_ERR(np_base))
  87 +               return PTR_ERR(np_base);
  88 +
  89 +       en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
  90 +
  91 +       val = readl(np_base + REG_NP_SCU_SSTR);
  92 +       val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
  93 +       writel(val, np_base + REG_NP_SCU_SSTR);
  94 +       val = readl(np_base + REG_NP_SCU_PCIC);
  95 +       writel(val | 3, np_base + REG_NP_SCU_PCIC);
  96 +
  97 +       return 0;
  98 +}
  99 +
 100  static int en7523_reset_update(struct reset_controller_dev *rcdev,
 101                                unsigned long id, bool assert)
 102  {
 103 @@ -543,31 +573,18 @@ static int en7523_clk_probe(struct platf
 104         struct device_node *node = pdev->dev.of_node;
 105         const struct en_clk_soc_data *soc_data;
 106         struct clk_hw_onecell_data *clk_data;
 107 -       void __iomem *base, *np_base;
 108         int r;
 109
 110 -       base = devm_platform_ioremap_resource(pdev, 0);
 111 -       if (IS_ERR(base))
 112 -               return PTR_ERR(base);
 113 -
 114 -       np_base = devm_platform_ioremap_resource(pdev, 1);
 115 -       if (IS_ERR(np_base))
 116 -               return PTR_ERR(np_base);
 117 -
 118 -       soc_data = device_get_match_data(&pdev->dev);
 119 -       if (soc_data->hw_init) {
 120 -               r = soc_data->hw_init(pdev, np_base);
 121 -               if (r)
 122 -                       return r;
 123 -       }
 124 -
 125         clk_data = devm_kzalloc(&pdev->dev,
 126                                 struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
 127                                 GFP_KERNEL);
 128         if (!clk_data)
 129                 return -ENOMEM;
 130
 131 -       en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
 132 +       soc_data = device_get_match_data(&pdev->dev);
 133 +       r = soc_data->hw_init(pdev, clk_data);
 134 +       if (r)
 135 +               return r;
 136
 137         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 138         if (r)
 139 @@ -590,6 +607,7 @@ static const struct en_clk_soc_data en75
 140                 .prepare = en7523_pci_prepare,
 141                 .unprepare = en7523_pci_unprepare,
 142         },
 143 +       .hw_init = en7523_clk_hw_init,
 144  };
 145
 146  static const struct en_clk_soc_data en7581_data = {