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1 From 4e3b2d236fe00f0e0b6c45dcb3cc7d84c2316424 Mon Sep 17 00:00:00 2001
2 From: Kamal Dasu <kdasu.kdev@gmail.com>
3 Date: Wed, 24 Aug 2016 18:04:25 -0400
4 Subject: [PATCH] spi: bcm-qspi: Add BSPI spi-nor flash controller driver
5
6 This change implements BSPI driver for Broadcom BRCMSTB, NS2,
7 NSP SoCs works in combination with the MSPI controller driver
8 and implements flash read acceleration and implements the
9 spi_flash_read() method. Both MSPI and BSPI controllers are
10 needed to access spi-nor flash.
11
12 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
13 Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
14 Signed-off-by: Mark Brown <broonie@kernel.org>
15 ---
16 drivers/spi/spi-bcm-qspi.c | 603 ++++++++++++++++++++++++++++++++++++++++++++-
17 drivers/spi/spi-bcm-qspi.h | 20 ++
18 2 files changed, 620 insertions(+), 3 deletions(-)
19
20 --- a/drivers/spi/spi-bcm-qspi.c
21 +++ b/drivers/spi/spi-bcm-qspi.c
22 @@ -38,6 +38,60 @@
23
24 #define DRIVER_NAME "bcm_qspi"
25
26 +
27 +/* BSPI register offsets */
28 +#define BSPI_REVISION_ID 0x000
29 +#define BSPI_SCRATCH 0x004
30 +#define BSPI_MAST_N_BOOT_CTRL 0x008
31 +#define BSPI_BUSY_STATUS 0x00c
32 +#define BSPI_INTR_STATUS 0x010
33 +#define BSPI_B0_STATUS 0x014
34 +#define BSPI_B0_CTRL 0x018
35 +#define BSPI_B1_STATUS 0x01c
36 +#define BSPI_B1_CTRL 0x020
37 +#define BSPI_STRAP_OVERRIDE_CTRL 0x024
38 +#define BSPI_FLEX_MODE_ENABLE 0x028
39 +#define BSPI_BITS_PER_CYCLE 0x02c
40 +#define BSPI_BITS_PER_PHASE 0x030
41 +#define BSPI_CMD_AND_MODE_BYTE 0x034
42 +#define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
43 +#define BSPI_BSPI_XOR_VALUE 0x03c
44 +#define BSPI_BSPI_XOR_ENABLE 0x040
45 +#define BSPI_BSPI_PIO_MODE_ENABLE 0x044
46 +#define BSPI_BSPI_PIO_IODIR 0x048
47 +#define BSPI_BSPI_PIO_DATA 0x04c
48 +
49 +/* RAF register offsets */
50 +#define BSPI_RAF_START_ADDR 0x100
51 +#define BSPI_RAF_NUM_WORDS 0x104
52 +#define BSPI_RAF_CTRL 0x108
53 +#define BSPI_RAF_FULLNESS 0x10c
54 +#define BSPI_RAF_WATERMARK 0x110
55 +#define BSPI_RAF_STATUS 0x114
56 +#define BSPI_RAF_READ_DATA 0x118
57 +#define BSPI_RAF_WORD_CNT 0x11c
58 +#define BSPI_RAF_CURR_ADDR 0x120
59 +
60 +/* Override mode masks */
61 +#define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0)
62 +#define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1)
63 +#define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2)
64 +#define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3)
65 +#define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4)
66 +
67 +#define BSPI_ADDRLEN_3BYTES 3
68 +#define BSPI_ADDRLEN_4BYTES 4
69 +
70 +#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
71 +
72 +#define BSPI_RAF_CTRL_START_MASK BIT(0)
73 +#define BSPI_RAF_CTRL_CLEAR_MASK BIT(1)
74 +
75 +#define BSPI_BPP_MODE_SELECT_MASK BIT(8)
76 +#define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
77 +
78 +#define BSPI_READ_LENGTH 256
79 +
80 /* MSPI register offsets */
81 #define MSPI_SPCR0_LSB 0x000
82 #define MSPI_SPCR0_MSB 0x004
83 @@ -108,8 +162,16 @@ struct bcm_qspi_parms {
84 u8 bits_per_word;
85 };
86
87 +struct bcm_xfer_mode {
88 + bool flex_mode;
89 + unsigned int width;
90 + unsigned int addrlen;
91 + unsigned int hp;
92 +};
93 +
94 enum base_type {
95 MSPI,
96 + BSPI,
97 CHIP_SELECT,
98 BASEMAX,
99 };
100 @@ -140,13 +202,28 @@ struct bcm_qspi {
101 struct bcm_qspi_parms last_parms;
102 struct qspi_trans trans_pos;
103 int curr_cs;
104 + int bspi_maj_rev;
105 + int bspi_min_rev;
106 + int bspi_enabled;
107 + struct spi_flash_read_message *bspi_rf_msg;
108 + u32 bspi_rf_msg_idx;
109 + u32 bspi_rf_msg_len;
110 + u32 bspi_rf_msg_status;
111 + struct bcm_xfer_mode xfer_mode;
112 u32 s3_strap_override_ctrl;
113 + bool bspi_mode;
114 bool big_endian;
115 int num_irqs;
116 struct bcm_qspi_dev_id *dev_ids;
117 struct completion mspi_done;
118 + struct completion bspi_done;
119 };
120
121 +static inline bool has_bspi(struct bcm_qspi *qspi)
122 +{
123 + return qspi->bspi_mode;
124 +}
125 +
126 /* Read qspi controller register*/
127 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
128 unsigned int offset)
129 @@ -161,6 +238,300 @@ static inline void bcm_qspi_write(struct
130 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
131 }
132
133 +/* BSPI helpers */
134 +static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
135 +{
136 + int i;
137 +
138 + /* this should normally finish within 10us */
139 + for (i = 0; i < 1000; i++) {
140 + if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
141 + return 0;
142 + udelay(1);
143 + }
144 + dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
145 + return -EIO;
146 +}
147 +
148 +static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
149 +{
150 + if (qspi->bspi_maj_rev < 4)
151 + return true;
152 + return false;
153 +}
154 +
155 +static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
156 +{
157 + bcm_qspi_bspi_busy_poll(qspi);
158 + /* Force rising edge for the b0/b1 'flush' field */
159 + bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
160 + bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
161 + bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
162 + bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
163 +}
164 +
165 +static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
166 +{
167 + return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
168 + BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
169 +}
170 +
171 +static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
172 +{
173 + u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
174 +
175 + /* BSPI v3 LR is LE only, convert data to host endianness */
176 + if (bcm_qspi_bspi_ver_three(qspi))
177 + data = le32_to_cpu(data);
178 +
179 + return data;
180 +}
181 +
182 +static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
183 +{
184 + bcm_qspi_bspi_busy_poll(qspi);
185 + bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
186 + BSPI_RAF_CTRL_START_MASK);
187 +}
188 +
189 +static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
190 +{
191 + bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
192 + BSPI_RAF_CTRL_CLEAR_MASK);
193 + bcm_qspi_bspi_flush_prefetch_buffers(qspi);
194 +}
195 +
196 +static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
197 +{
198 + u32 *buf = (u32 *)qspi->bspi_rf_msg->buf;
199 + u32 data = 0;
200 +
201 + dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_msg,
202 + qspi->bspi_rf_msg->buf, qspi->bspi_rf_msg_len);
203 + while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
204 + data = bcm_qspi_bspi_lr_read_fifo(qspi);
205 + if (likely(qspi->bspi_rf_msg_len >= 4) &&
206 + IS_ALIGNED((uintptr_t)buf, 4)) {
207 + buf[qspi->bspi_rf_msg_idx++] = data;
208 + qspi->bspi_rf_msg_len -= 4;
209 + } else {
210 + /* Read out remaining bytes, make sure*/
211 + u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_msg_idx];
212 +
213 + data = cpu_to_le32(data);
214 + while (qspi->bspi_rf_msg_len) {
215 + *cbuf++ = (u8)data;
216 + data >>= 8;
217 + qspi->bspi_rf_msg_len--;
218 + }
219 + }
220 + }
221 +}
222 +
223 +static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
224 + int bpp, int bpc, int flex_mode)
225 +{
226 + bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
227 + bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
228 + bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
229 + bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
230 + bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
231 +}
232 +
233 +static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, int width,
234 + int addrlen, int hp)
235 +{
236 + int bpc = 0, bpp = 0;
237 + u8 command = SPINOR_OP_READ_FAST;
238 + int flex_mode = 1, rv = 0;
239 + bool spans_4byte = false;
240 +
241 + dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
242 + width, addrlen, hp);
243 +
244 + if (addrlen == BSPI_ADDRLEN_4BYTES) {
245 + bpp = BSPI_BPP_ADDR_SELECT_MASK;
246 + spans_4byte = true;
247 + }
248 +
249 + bpp |= 8;
250 +
251 + switch (width) {
252 + case SPI_NBITS_SINGLE:
253 + if (addrlen == BSPI_ADDRLEN_3BYTES)
254 + /* default mode, does not need flex_cmd */
255 + flex_mode = 0;
256 + else
257 + command = SPINOR_OP_READ4_FAST;
258 + break;
259 + case SPI_NBITS_DUAL:
260 + bpc = 0x00000001;
261 + if (hp) {
262 + bpc |= 0x00010100; /* address and mode are 2-bit */
263 + bpp = BSPI_BPP_MODE_SELECT_MASK;
264 + command = OPCODE_DIOR;
265 + if (spans_4byte)
266 + command = OPCODE_DIOR_4B;
267 + } else {
268 + command = SPINOR_OP_READ_1_1_2;
269 + if (spans_4byte)
270 + command = SPINOR_OP_READ4_1_1_2;
271 + }
272 + break;
273 + case SPI_NBITS_QUAD:
274 + bpc = 0x00000002;
275 + if (hp) {
276 + bpc |= 0x00020200; /* address and mode are 4-bit */
277 + bpp = 4; /* dummy cycles */
278 + bpp |= BSPI_BPP_ADDR_SELECT_MASK;
279 + command = OPCODE_QIOR;
280 + if (spans_4byte)
281 + command = OPCODE_QIOR_4B;
282 + } else {
283 + command = SPINOR_OP_READ_1_1_4;
284 + if (spans_4byte)
285 + command = SPINOR_OP_READ4_1_1_4;
286 + }
287 + break;
288 + default:
289 + rv = -EINVAL;
290 + break;
291 + }
292 +
293 + if (rv == 0)
294 + bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc,
295 + flex_mode);
296 +
297 + return rv;
298 +}
299 +
300 +static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, int width,
301 + int addrlen, int hp)
302 +{
303 + u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
304 +
305 + dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
306 + width, addrlen, hp);
307 +
308 + switch (width) {
309 + case SPI_NBITS_SINGLE:
310 + /* clear quad/dual mode */
311 + data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
312 + BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
313 + break;
314 +
315 + case SPI_NBITS_QUAD:
316 + /* clear dual mode and set quad mode */
317 + data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
318 + data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
319 + break;
320 + case SPI_NBITS_DUAL:
321 + /* clear quad mode set dual mode */
322 + data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
323 + data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
324 + break;
325 + default:
326 + return -EINVAL;
327 + }
328 +
329 + if (addrlen == BSPI_ADDRLEN_4BYTES)
330 + /* set 4byte mode*/
331 + data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
332 + else
333 + /* clear 4 byte mode */
334 + data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
335 +
336 + /* set the override mode */
337 + data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
338 + bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
339 + bcm_qspi_bspi_set_xfer_params(qspi, SPINOR_OP_READ_FAST, 0, 0, 0);
340 +
341 + return 0;
342 +}
343 +
344 +static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
345 + int width, int addrlen, int hp)
346 +{
347 + int error = 0;
348 +
349 + /* default mode */
350 + qspi->xfer_mode.flex_mode = true;
351 +
352 + if (!bcm_qspi_bspi_ver_three(qspi)) {
353 + u32 val, mask;
354 +
355 + val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
356 + mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
357 + if (val & mask || qspi->s3_strap_override_ctrl & mask) {
358 + qspi->xfer_mode.flex_mode = false;
359 + bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE,
360 + 0);
361 +
362 + if ((val | qspi->s3_strap_override_ctrl) &
363 + BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL)
364 + width = SPI_NBITS_DUAL;
365 + else if ((val | qspi->s3_strap_override_ctrl) &
366 + BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD)
367 + width = SPI_NBITS_QUAD;
368 +
369 + error = bcm_qspi_bspi_set_override(qspi, width, addrlen,
370 + hp);
371 + }
372 + }
373 +
374 + if (qspi->xfer_mode.flex_mode)
375 + error = bcm_qspi_bspi_set_flex_mode(qspi, width, addrlen, hp);
376 +
377 + if (error) {
378 + dev_warn(&qspi->pdev->dev,
379 + "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
380 + width, addrlen, hp);
381 + } else if (qspi->xfer_mode.width != width ||
382 + qspi->xfer_mode.addrlen != addrlen ||
383 + qspi->xfer_mode.hp != hp) {
384 + qspi->xfer_mode.width = width;
385 + qspi->xfer_mode.addrlen = addrlen;
386 + qspi->xfer_mode.hp = hp;
387 + dev_dbg(&qspi->pdev->dev,
388 + "cs:%d %d-lane output, %d-byte address%s\n",
389 + qspi->curr_cs,
390 + qspi->xfer_mode.width,
391 + qspi->xfer_mode.addrlen,
392 + qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
393 + }
394 +
395 + return error;
396 +}
397 +
398 +static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
399 +{
400 + if (!has_bspi(qspi) || (qspi->bspi_enabled))
401 + return;
402 +
403 + qspi->bspi_enabled = 1;
404 + if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
405 + return;
406 +
407 + bcm_qspi_bspi_flush_prefetch_buffers(qspi);
408 + udelay(1);
409 + bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
410 + udelay(1);
411 +}
412 +
413 +static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
414 +{
415 + if (!has_bspi(qspi) || (!qspi->bspi_enabled))
416 + return;
417 +
418 + qspi->bspi_enabled = 0;
419 + if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
420 + return;
421 +
422 + bcm_qspi_bspi_busy_poll(qspi);
423 + bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
424 + udelay(1);
425 +}
426 +
427 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
428 {
429 u32 data = 0;
430 @@ -298,6 +669,8 @@ static void read_from_hw(struct bcm_qspi
431 struct qspi_trans tp;
432 int slot;
433
434 + bcm_qspi_disable_bspi(qspi);
435 +
436 if (slots > MSPI_NUM_CDRAM) {
437 /* should never happen */
438 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
439 @@ -368,6 +741,7 @@ static int write_to_hw(struct bcm_qspi *
440 int slot = 0, tstatus = 0;
441 u32 mspi_cdram = 0;
442
443 + bcm_qspi_disable_bspi(qspi);
444 tp = qspi->trans_pos;
445 bcm_qspi_update_parms(qspi, spi, tp.trans);
446
447 @@ -414,6 +788,9 @@ static int write_to_hw(struct bcm_qspi *
448 write_cdram_slot(qspi, slot - 1, mspi_cdram);
449 }
450
451 + if (has_bspi(qspi))
452 + bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
453 +
454 /* Must flush previous writes before starting MSPI operation */
455 mb();
456 /* Set cont | spe | spifie */
457 @@ -423,6 +800,118 @@ done:
458 return slot;
459 }
460
461 +static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
462 + struct spi_flash_read_message *msg)
463 +{
464 + struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
465 + u32 addr = 0, len, len_words;
466 + int ret = 0;
467 + unsigned long timeo = msecs_to_jiffies(100);
468 +
469 + if (bcm_qspi_bspi_ver_three(qspi))
470 + if (msg->addr_width == BSPI_ADDRLEN_4BYTES)
471 + return -EIO;
472 +
473 + bcm_qspi_chip_select(qspi, spi->chip_select);
474 + bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
475 +
476 + /*
477 + * when using flex mode mode we need to send
478 + * the upper address byte to bspi
479 + */
480 + if (bcm_qspi_bspi_ver_three(qspi) == false) {
481 + addr = msg->from & 0xff000000;
482 + bcm_qspi_write(qspi, BSPI,
483 + BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
484 + }
485 +
486 + if (!qspi->xfer_mode.flex_mode)
487 + addr = msg->from;
488 + else
489 + addr = msg->from & 0x00ffffff;
490 +
491 + /* set BSPI RAF buffer max read length */
492 + len = msg->len;
493 + if (len > BSPI_READ_LENGTH)
494 + len = BSPI_READ_LENGTH;
495 +
496 + if (bcm_qspi_bspi_ver_three(qspi) == true)
497 + addr = (addr + 0xc00000) & 0xffffff;
498 +
499 + reinit_completion(&qspi->bspi_done);
500 + bcm_qspi_enable_bspi(qspi);
501 + len_words = (len + 3) >> 2;
502 + qspi->bspi_rf_msg = msg;
503 + qspi->bspi_rf_msg_status = 0;
504 + qspi->bspi_rf_msg_idx = 0;
505 + qspi->bspi_rf_msg_len = len;
506 + dev_dbg(&qspi->pdev->dev, "bspi xfr addr 0x%x len 0x%x", addr, len);
507 +
508 + bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
509 + bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
510 + bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
511 +
512 + /* Must flush previous writes before starting BSPI operation */
513 + mb();
514 +
515 + bcm_qspi_bspi_lr_start(qspi);
516 + if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
517 + dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
518 + ret = -ETIMEDOUT;
519 + } else {
520 + /* set the return length for the caller */
521 + msg->retlen = len;
522 + }
523 +
524 + return ret;
525 +}
526 +
527 +static int bcm_qspi_flash_read(struct spi_device *spi,
528 + struct spi_flash_read_message *msg)
529 +{
530 + struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
531 + int ret = 0;
532 + bool mspi_read = false;
533 + u32 io_width, addrlen, addr, len;
534 + u_char *buf;
535 +
536 + buf = msg->buf;
537 + addr = msg->from;
538 + len = msg->len;
539 +
540 + if (bcm_qspi_bspi_ver_three(qspi) == true) {
541 + /*
542 + * The address coming into this function is a raw flash offset.
543 + * But for BSPI <= V3, we need to convert it to a remapped BSPI
544 + * address. If it crosses a 4MB boundary, just revert back to
545 + * using MSPI.
546 + */
547 + addr = (addr + 0xc00000) & 0xffffff;
548 +
549 + if ((~ADDR_4MB_MASK & addr) ^
550 + (~ADDR_4MB_MASK & (addr + len - 1)))
551 + mspi_read = true;
552 + }
553 +
554 + /* non-aligned and very short transfers are handled by MSPI */
555 + if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
556 + len < 4)
557 + mspi_read = true;
558 +
559 + if (mspi_read)
560 + /* this will make the m25p80 read to fallback to mspi read */
561 + return -EAGAIN;
562 +
563 + io_width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
564 + addrlen = msg->addr_width;
565 + ret = bcm_qspi_bspi_set_mode(qspi, io_width, addrlen, -1);
566 +
567 + if (!ret)
568 + ret = bcm_qspi_bspi_flash_read(spi, msg);
569 +
570 + return ret;
571 +}
572 +
573 static int bcm_qspi_transfer_one(struct spi_master *master,
574 struct spi_device *spi,
575 struct spi_transfer *trans)
576 @@ -469,13 +958,76 @@ static irqreturn_t bcm_qspi_mspi_l2_isr(
577 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
578 complete(&qspi->mspi_done);
579 return IRQ_HANDLED;
580 - } else {
581 - return IRQ_NONE;
582 }
583 +
584 + return IRQ_NONE;
585 +}
586 +
587 +static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
588 +{
589 + struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
590 + struct bcm_qspi *qspi = qspi_dev_id->dev;
591 + u32 status;
592 +
593 + if (qspi->bspi_enabled && qspi->bspi_rf_msg) {
594 + bcm_qspi_bspi_lr_data_read(qspi);
595 + if (qspi->bspi_rf_msg_len == 0) {
596 + qspi->bspi_rf_msg = NULL;
597 + if (qspi->bspi_rf_msg_status)
598 + bcm_qspi_bspi_lr_clear(qspi);
599 + else
600 + bcm_qspi_bspi_flush_prefetch_buffers(qspi);
601 + }
602 + }
603 +
604 + status = (qspi_dev_id->irqp->mask & INTR_BSPI_LR_SESSION_DONE_MASK);
605 + if (qspi->bspi_enabled && status && qspi->bspi_rf_msg_len == 0)
606 + complete(&qspi->bspi_done);
607 +
608 + return IRQ_HANDLED;
609 +}
610 +
611 +static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
612 +{
613 + struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
614 + struct bcm_qspi *qspi = qspi_dev_id->dev;
615 +
616 + dev_err(&qspi->pdev->dev, "BSPI INT error\n");
617 + qspi->bspi_rf_msg_status = -EIO;
618 + complete(&qspi->bspi_done);
619 + return IRQ_HANDLED;
620 }
621
622 static const struct bcm_qspi_irq qspi_irq_tab[] = {
623 {
624 + .irq_name = "spi_lr_fullness_reached",
625 + .irq_handler = bcm_qspi_bspi_lr_l2_isr,
626 + .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
627 + },
628 + {
629 + .irq_name = "spi_lr_session_aborted",
630 + .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
631 + .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
632 + },
633 + {
634 + .irq_name = "spi_lr_impatient",
635 + .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
636 + .mask = INTR_BSPI_LR_IMPATIENT_MASK,
637 + },
638 + {
639 + .irq_name = "spi_lr_session_done",
640 + .irq_handler = bcm_qspi_bspi_lr_l2_isr,
641 + .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
642 + },
643 +#ifdef QSPI_INT_DEBUG
644 + /* this interrupt is for debug purposes only, dont request irq */
645 + {
646 + .irq_name = "spi_lr_overread",
647 + .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
648 + .mask = INTR_BSPI_LR_OVERREAD_MASK,
649 + },
650 +#endif
651 + {
652 .irq_name = "mspi_done",
653 .irq_handler = bcm_qspi_mspi_l2_isr,
654 .mask = INTR_MSPI_DONE_MASK,
655 @@ -487,6 +1039,24 @@ static const struct bcm_qspi_irq qspi_ir
656 },
657 };
658
659 +static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
660 +{
661 + u32 val = 0;
662 +
663 + val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
664 + qspi->bspi_maj_rev = (val >> 8) & 0xff;
665 + qspi->bspi_min_rev = val & 0xff;
666 + if (!(bcm_qspi_bspi_ver_three(qspi))) {
667 + /* Force mapping of BSPI address -> flash offset */
668 + bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
669 + bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
670 + }
671 + qspi->bspi_enabled = 1;
672 + bcm_qspi_disable_bspi(qspi);
673 + bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
674 + bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
675 +}
676 +
677 static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
678 {
679 struct bcm_qspi_parms parms;
680 @@ -501,11 +1071,17 @@ static void bcm_qspi_hw_init(struct bcm_
681 parms.bits_per_word = 8;
682 parms.speed_hz = qspi->max_speed_hz;
683 bcm_qspi_hw_set_parms(qspi, &parms);
684 +
685 + if (has_bspi(qspi))
686 + bcm_qspi_bspi_init(qspi);
687 }
688
689 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
690 {
691 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
692 + if (has_bspi(qspi))
693 + bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
694 +
695 }
696
697 static const struct of_device_id bcm_qspi_of_match[] = {
698 @@ -515,7 +1091,7 @@ static const struct of_device_id bcm_qsp
699 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
700
701 int bcm_qspi_probe(struct platform_device *pdev,
702 - struct bcm_qspi_soc_intc *soc)
703 + struct bcm_qspi_soc_intc *soc_intc)
704 {
705 struct device *dev = &pdev->dev;
706 struct bcm_qspi *qspi;
707 @@ -549,6 +1125,7 @@ int bcm_qspi_probe(struct platform_devic
708 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
709 master->setup = bcm_qspi_setup;
710 master->transfer_one = bcm_qspi_transfer_one;
711 + master->spi_flash_read = bcm_qspi_flash_read;
712 master->cleanup = bcm_qspi_cleanup;
713 master->dev.of_node = dev->of_node;
714 master->num_chipselect = NUM_CHIPSELECT;
715 @@ -573,6 +1150,20 @@ int bcm_qspi_probe(struct platform_devic
716 goto qspi_probe_err;
717 }
718
719 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
720 + if (res) {
721 + qspi->base[BSPI] = devm_ioremap_resource(dev, res);
722 + if (IS_ERR(qspi->base[BSPI])) {
723 + ret = PTR_ERR(qspi->base[BSPI]);
724 + goto qspi_probe_err;
725 + }
726 + qspi->bspi_mode = true;
727 + } else {
728 + qspi->bspi_mode = false;
729 + }
730 +
731 + dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
732 +
733 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
734 if (res) {
735 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
736 @@ -635,9 +1226,15 @@ int bcm_qspi_probe(struct platform_devic
737
738 bcm_qspi_hw_init(qspi);
739 init_completion(&qspi->mspi_done);
740 + init_completion(&qspi->bspi_done);
741 qspi->curr_cs = -1;
742
743 platform_set_drvdata(pdev, qspi);
744 +
745 + qspi->xfer_mode.width = -1;
746 + qspi->xfer_mode.addrlen = -1;
747 + qspi->xfer_mode.hp = -1;
748 +
749 ret = devm_spi_register_master(&pdev->dev, master);
750 if (ret < 0) {
751 dev_err(dev, "can't register master\n");
752 --- a/drivers/spi/spi-bcm-qspi.h
753 +++ b/drivers/spi/spi-bcm-qspi.h
754 @@ -20,6 +20,26 @@
755 #include <linux/types.h>
756 #include <linux/io.h>
757
758 +/* BSPI interrupt masks */
759 +#define INTR_BSPI_LR_OVERREAD_MASK BIT(4)
760 +#define INTR_BSPI_LR_SESSION_DONE_MASK BIT(3)
761 +#define INTR_BSPI_LR_IMPATIENT_MASK BIT(2)
762 +#define INTR_BSPI_LR_SESSION_ABORTED_MASK BIT(1)
763 +#define INTR_BSPI_LR_FULLNESS_REACHED_MASK BIT(0)
764 +
765 +#define BSPI_LR_INTERRUPTS_DATA \
766 + (INTR_BSPI_LR_SESSION_DONE_MASK | \
767 + INTR_BSPI_LR_FULLNESS_REACHED_MASK)
768 +
769 +#define BSPI_LR_INTERRUPTS_ERROR \
770 + (INTR_BSPI_LR_OVERREAD_MASK | \
771 + INTR_BSPI_LR_IMPATIENT_MASK | \
772 + INTR_BSPI_LR_SESSION_ABORTED_MASK)
773 +
774 +#define BSPI_LR_INTERRUPTS_ALL \
775 + (BSPI_LR_INTERRUPTS_ERROR | \
776 + BSPI_LR_INTERRUPTS_DATA)
777 +
778 /* MSPI Interrupt masks */
779 #define INTR_MSPI_HALTED_MASK BIT(6)
780 #define INTR_MSPI_DONE_MASK BIT(5)
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