git.openwrt.org Git - openwrt/staging/dangole.git/blob

   1 From 502af2ba683831fb4c05bd887374053d17376c87 Mon Sep 17 00:00:00 2001
   2 From: P33M <p33m@github.com>
   3 Date: Fri, 21 Sep 2018 14:05:09 +0100
   4 Subject: [PATCH 420/454] dwc_otg: fiq_fsm: fix incorrect DMA register offset
   5  calculation
   6
   7 Rationalise the offset and update all call sites.
   8
   9 Fixes https://github.com/raspberrypi/linux/issues/2408
  10 ---
  11  drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 8 ++++----
  12  drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 2 +-
  13  2 files changed, 5 insertions(+), 5 deletions(-)
  14
  15 --- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
  16 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
  17 @@ -250,7 +250,7 @@ static int notrace fiq_increment_dma_buf
  18                 BUG();
  19
  20         hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
  21 -       FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
  22 +       FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
  23         st->channel[n].dma_info.index = i;
  24         return 0;
  25  }
  26 @@ -302,7 +302,7 @@ static int notrace fiq_iso_out_advance(s
  27
  28         /* New DMA address - address of bounce buffer referred to in index */
  29         hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
  30 -       //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
  31 +       //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);
  32         //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
  33         fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
  34         fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
  35 @@ -317,7 +317,7 @@ static int notrace fiq_iso_out_advance(s
  36         st->channel[n].dma_info.index++;
  37         FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
  38         FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
  39 -       FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
  40 +       FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
  41         return last;
  42  }
  43
  44 @@ -564,7 +564,7 @@ static int notrace noinline fiq_fsm_upda
  45
  46         /* grab the next DMA address offset from the array */
  47         hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
  48 -       FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
  49 +       FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
  50
  51         /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
  52          * the core needs to be told to send the correct number. Caution: for IN transfers,
  53 --- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
  54 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
  55 @@ -94,7 +94,7 @@ do {                                                  \
  56  #define HC_START       0x500
  57  #define HC_OFFSET      0x020
  58
  59 -#define HC_DMA         0x514
  60 +#define HC_DMA         0x14
  61
  62  #define HCCHAR         0x00
  63  #define HCSPLT         0x04